ZHCSGQ7C September 2017 – May 2019 TDP142
PRODUCTION DATA.
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| VCC | 1, 6, 20, 28 | P | 3.3-V Power Supply. |
| DPEQ1 | 2 | 4 Level I | DisplayPort Receiver EQ control. This along with DPEQ0 will select the DisplayPort receiver equalization gain. Refer to Table 2 for equalization settings. |
| RSVD1 | 3 | I | Reserved.(1) |
| RSVD2 | 4 | O | Reserved.(1) |
| RSVD3 | 5 | O | Reserved.(1) |
| RSVD4 | 7 | I | Reserved.(1) |
| RSVD5 | 8 | I | Reserved.(1) |
| INDP0p | 9 | I | DP Differential positive input for DisplayPort Lane 0. |
| INDP0n | 10 | I | DP Differential negative input for DisplayPort Lane 0. |
| A0 | 11 | 4 Level I | When I2C_EN = 0, leave the pin unconnected. When I2C_EN is not ‘0’, this pin will also set the TDP142 I2C address. See Table 4. If I2C_EN = “F”, then this pin must be set to “F” or “0”. |
| INDP1p | 12 | Diff I | DP Differential positive input for DisplayPort Lane 1. |
| INDP1n | 13 | Diff I | DP Differential negative input for DisplayPort Lane 1. |
| DPEQ0/A1 | 14 | 4 Level I | DisplayPort Receiver EQ control. This along with DPEQ1 will select the DisplayPort receiver equalization gain. Refer to Table 2 for equalization settings. When I2C_EN is not ‘0’, this pin will also set the TDP142 I2C address. See Table 4. |
| INDP2p | 15 | Diff I | DP Differential positive input for DisplayPort Lane 2. |
| INDP2n | 16 | Diff I | DP Differential negative input for DisplayPort Lane 2. |
| I2C_EN | 17 | 4 Level I | I2C Programming Mode or GPIO Programming Select. I2C is only disabled when this pin is ‘0".
0 = GPIO mode (I2C disabled). R = TI Test Mode (I2C enabled at 3.3 V). F = I2C enabled at 1.8 V. 1 = I2C enabled at 3.3 V. |
| INDP3p | 18 | Diff I | DP Differential positive input for DisplayPort Lane 3. |
| INDP3n | 19 | Diff I | DP Differential negative input for DisplayPort Lane 3. |
| TEST1/SCL | 21 | 2 Level I | When I2C_EN=’0’, pull down with 10k or directly connect to ground. Otherwise this pin is I2C clock. . When used for I2C clock pullup to I2C master's VCC I2C supply. |
| TEST2/SDA | 22 | 2 Level I | When I2C_EN=’0’ , pull down with 10k or directly connect to ground. Otherwise this pin is I2C data. When used for I2C data pullup to I2C master's VCC I2C supply. |
| DPEN/HPDIN | 23 | 2 Level I
(Failsafe) (PD) |
DP Enable Pin. When I2C_EN = ‘0’, this pin will enable or disable DisplayPort functionality. Otherwise, when I2C_EN is not "0", DisplayPort functionality is enabled and disabled through I2C registers.
L = DisplayPort Disabled. (Pull-down with 10k resistor) H = DisplayPort Enabled. (Pull-up with10k resistor) When I2C_EN is not "0" this pin is an input for Hot Plug Detect (HPD) received from DisplayPort sink. When this HPDIN is low for greater than 2 ms, all DisplayPort lanes are disabled. |
| AUXp | 24 | I/O, CMOS | This pin along with AUXN is used by the TDP142 for AUX snooping. See the Application and Implementation section for more detail. |
| AUXn | 25 | I/O, CMOS | This pin along with AUXP is used by the TDP142 for AUX snooping. See the Application and Implementation section for more detail. |
| RSVD6 | 26 | I/O, CMOS | Reserved.(1) |
| RSVD7 | 27 | I/O, CMOS | Reserved.(1) |
| SNOOPENZ/RSVD8 | 29(2) | I/O
(PD) |
When I2C_EN ! = 0, this pin is reserved. When I2C_EN = 0 , this pin is SNOOPENZ (L = AUX snoop enabled and H = AUX snoop disabled with all lanes active). |
| OUTDP3p | 30 | Diff O | DP Differential positive output for DisplayPort Lane 3. |
| OUTDP3n | 31 | Diff O | DP Differential negative output for DisplayPort Lane 3. |
| HPDIN/RSVD9 | 32(2) | I/O
(PD) |
When I2C_EN ! = 0, this pin is reserved. When I2C_EN = 0, this pin is an input for Hot Plug Detect received from DisplayPort sink. When HPDIN is low for greater than 2ms, all DisplayPort lanes are disabled. |
| OUTDP2p | 33 | Diff O | DP Differential positive output for DisplayPort Lane 2. |
| OUTDP2n | 34 | Diff O | DP Differential negative output for DisplayPort Lane 2. |
| RSVD10 | 35 | I | Reserved.(1) |
| OUTDP1n | 36 | Diff O | DP Differential negative output for DisplayPort Lane 1. |
| OUTDP1p | 37 | Diff O | DP Differential positive output for DisplayPort Lane 1. |
| RSVD11 | 38 | I | Reserved.(1) |
| OUTDP0n | 39 | Diff O | DP Differential negative output for DisplayPort Lane 0. |
| OUTDP0p | 40 | Diff O | DP Differential positive output for DisplayPort Lane 0. |
| GND | Thermal Pad | G | Ground. |