ZHCSGQ7C September 2017 – May 2019 TDP142
PRODUCTION DATA.
The TDP142 supports up to 4 DisplayPort lanes at data rates up to 8.1Gbps (HBR3). The TDP142 monitors the native AUX traffic as it traverses between DisplayPort source and DisplayPort sink. For the purposes of reducing power, the TDP142 manages the number of active DisplayPort lanes based on the content of the AUX transactions. The TDP142 snoops native AUX writes to DisplayPort sink’s DPCD registers 0x00101 (LANE_COUNT_SET) and 0x00600 (SET_POWER_STATE). TDP142 disables/enables lanes based on value written to LANE_COUNT_SET. The TDP142 disables all lanes when SET_POWER_STATE is in the D3. Otherwise active lanes will be based on value of LANE_COUNT_SET.
DisplayPort AUX snooping is enabled by default but can be disabled by changing the AUX_SNOOP_DISABLE register. Once AUX snoop is disabled, management of TDP142 DisplayPort lanes are controlled through various configuration registers. When TDP142 is enabled for GPIO mode (I2C_EN = "0"), the SNOOPENZ pin can be used to disable AUX snooping. When SNOOPENZ pin is high, the AUX snooping functionality is disabled and all four DisplayPort lanes will be active.