ZHCSK43A August 2019 – November 2019 TCAN4551-Q1
PRODUCTION DATA.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RSVD | TEFL | EFF | |||||
| R | R | R | |||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RSVD | EFPI[4:0] | ||||||
| R | R | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RSVD | REFGI[4:0] | ||||||
| R | R | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSVD | EFFL[5:0] | ||||||
| R | R | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:26 | RSVD | R | 0x0 | Reserved |
| 25 | TEFL | R | 0 | Tx Event FIFO Element Lost
This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is reset, this bit is also reset. 0 - No Tx Event FIFO element lost 1 - Tx Event FIFO element lost, also set after write attempt to Tx Event FIFO of size zero. |
| 24 | EFF | R | 0 | Event FIFO Full
0 - Tx Event FIFO not full 1 - Tx Event FIFO full |
| 23:21 | RSVD | R | 0x0 | Reserved |
| 20:16 | EFPI[4:0] | R | 0x0 | Event FIFO Put Index
Tx Event FIFO write index pointer, range 0 to 31. |
| 15:13 | RSVD | R | 0x0 | Reserved |
| 12:8 | REFGI[4:0] | R | 0x0 | Event FIFO Get Index
Tx Event FIFO read index pointer, range 0 to 31. |
| 7:6 | RSVD | R | 0x0 | Reserved |
| 5:0 | EFFL[5:0] | R | 0x0 | Event FIFO Fill Level
Number of elements stored in Tx Event FIFO, range 0 to 32 |