ZHCSK43A August 2019 – November 2019 TCAN4551-Q1
PRODUCTION DATA.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| ND63 | ND62 | ND61 | ND60 | ND59 | ND58 | ND57 | ND56 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| ND55 | ND54 | ND53 | ND52 | ND51 | ND50 | ND49 | ND48 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ND47 | ND46 | ND45 | ND44 | ND43 | ND42 | ND41 | ND40 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ND39 | ND38 | ND37 | ND36 | ND35 | ND34 | ND33 | ND32 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | ND63 to ND32 | R/W | 0 | The register holds the New Data flags of Rx Buffers 32 to 63. The flags are set when the respective Rx Buffer has been updated from a received frame. The flags remain set until the Host clears them. A flag is cleared by writing a ’1’ to the corresponding bit position. Writing a ’0’ has no effect. A hard reset will clear the register
0 - Rx Buffer not updated 1 - Rx Buffer updated from new message |