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ZHCSPG0 December 2021 TCAN1167-Q1

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DMT|14
- MPSS087B

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

DMT|14
- QFND638

訂購(gòu)信息

zhcspg0_oa

7.7 Electrical Characteristics

Over recommended operating conditions with T_J = –40°C to 150°C, unless otherwise noted. All typical values are taken at 25°C, V_SUP = 12 V, and R_L = 60 ?

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
CAN Driver Electrical Characteristics
V_O(D)	Dominant output voltage Bus biasing active	CANH	TXD = 0 V, 50 ≤ R_L ≤ 65 ?, C_L = open, R_CM= open See Figure 8-2	2.75		4.5	V
V_O(D)	Dominant output voltage Bus biasing active	CANL		0.5		2.25	V
V_O(R)	Recessive output voltage Bus biasing active		TXD = V_CCOUT, R_L = open (no load), R_CM = open See Figure 8-2	2		3	V
V_SYM	Driver symmetry Bus biasing active (V_O(CANH) + V_O(CANL)) / V_CCOUT		R_L = 60 ?, C_SPLIT = 4.7 nF, C_L = Open, R_CM = Open, TXD = 250 kHz, 1 Mhz, 2.5 MHz See Figure 8-2	0.9		1.1	V/V
V_{SYM_DC}	DC Driver symmetry Bus biasing active V_CCOUT – V_O(CANH) – V_O(CANL)		R_L = 60 ?, C_L = open See Figure 8-2	–400		400	mV
V_OD(DOM)	Differential output voltage Bus biasing active Dominant	CANH - CANL	TXD = 0 V, 50 ? ≤ R_L ≤ 65 ?, C_L = open See Figure 8-2	1.5		3	V
	Differential output voltage Bus biasing active Dominant	CANH - CANL	TXD = 0 V, 45 ? ≤ R_L ≤ 70 ?, CL = open See Figure 8-2	1.4		3.3	V
	Differential output voltage Bus biasing active Dominant	CANH - CANL	TXD = 0 V, R_L = 2240 ?, C_L = open See Figure 8-2	1.5		5	V
V_OD(REC)	Differential output voltage Bus biasing active Bus biasing inactive Recessive	CANH - CANL	TXD = V_CCOUT, R_L = open ?, C_L = open See Figure 8-2	–50		50	mV
V_O(INACT)	Pin output voltage Bus biasing inactive	CANH	TXD = V_CCOUT R_L = open (no load), C_L = open See Figure 8-2	-0.1		0.1	V
V_O(INACT)	Pin output voltage Bus biasing inactive	CANL	TXD = V_CCOUT R_L = open (no load), C_L = open See Figure 8-2	-0.1		0.1	V
V_OD(STB)	Differential output voltage Bus biasing inactive	CANH - CANL	TXD = V_CCOUT R_L = open (no load), C_L = open See Figure 8-2	-0.2		0.2	V
I_OS(DOM)	Short-circuit steady-state output current Bus biasing active Dominant		TXD = 0 V -15 V ≤ V_(CANH) ≤ 40 V See Figure 8-2 and Figure 8-8	–75			mA
I_OS(DOM)	Short-circuit steady-state output current Bus biasing active Dominant		TXD = 0 V -15 V ≤ V_(CANL) ≤ 40 V See Figure 8-2 and Figure 8-8			75	mA
I_OS(REC)	Short-circuit steady-state output current Bus biasing active Recessive		V_BUS = CANH = CANL -27 V ≤ V_BUS ≤ 42 V See Figure 8-2 and Figure 8-8	–3		3	mA
CAN Receiver Electrical Characteristics
V_IT(DOM)	Receiver dominant state input voltage range Bus biasing active		-12 V ≤ V_CM≤ 12 V See Figure 8-3 and Table 9-14	0.9		8	V
V_IT(REC)	Receiver recessive state input voltage range Bus biasing active		-12 V ≤ V_CM≤ 12 V See Figure 8-3 and Table 9-14	-3		0.5	V
V_HYS	Hysteresis voltage for input threshold Bus biasing active		See Figure 8-3 and Table 9-14	80	140		mV
V_DIFF(MAX)	Maximum rating of V_DIFF			-5		10	V
V_DIFF(DOM)	Receiver dominant state input voltage range Bus biasing inactive		-12 V ≤ V_CM≤ 12 V See Figure 8-3 and Table 9-14	1.150		8	V
V_DIFF(REC)	Receiver recessive state input voltage range Bus biasing inactive		-12 V ≤ V_CM≤ 12 V See Figure 8-3 and Table 9-14	-3		0.4	V
V_CM	Common mode range		See Figure 8-3 and Table 9-14	–12		12	V
I_OFF(LKG)	Power-off (unpowered) bus input leakage current		V_SUP = 0 V, CANH = CANL = 5 V			2.5	μA
C_I	Input capacitance to ground (CANH or CANL)⁽¹⁾		TXD = V_CCOUT			20	pF
C_ID	Differential input capacitance⁽¹⁾		TXD = V_CCOUT			10	pF
R_ID	Differential input resistance		TXD = V_CCOUT -12 V ≤ V_CM ≤ 12 V	50		100	k?
R_IN	Input resistance (CANH or CANL)		TXD = V_CCOUT -12 V ≤ V_CM ≤ 12 V	25		50	k?
R_IN(M)	Input resistance matching: [1 – R_IN(CANH) / R_IN(CANL)] × 100%		V_(CANH) = V_(CANL)= 5 V	–1		1	%
TXD Input Characteristics
V_IH	High level input voltage			0.7			V_CCOUT
V_IL	Low level input voltage					0.3	V_CCOUT
I_IH	High level input leakage current		TXD = V_CCOUT	–1	0	1	μA
I_IL	Low level input leakage current		TXD = 0 V	–130		–15	μA
R_PU	Pull-up resistance			40	60	80	k?
I_LKG(OFF)	Unpowered leakage current		TXD = 5.5 V, V_SUP = 0 V	–1	0	1	μA
C_I	Input Capacitance		V_IN = 0.4 x sin(2 × π × 2 × 10⁶ × t) + 2.5 V		5		pF
RXD Output Characteristics
V_OH	High level output voltage		I_O = –2 mA.	0.8			V_CCOUT
V_OL	Low level output voltage		I_O = 2 mA.			0.2	V_CCOUT
R_PU	Pull-up resistance			40	60	80	k?
I_LKG(OFF)	Unpowered leakage curret		RXD = 5.5 V, V_SUP = 0 V	-5		5	μA
INH Output Characteristics
ΔV_H	High level voltage drop INH with respect to V_SUP		I_INH = –6 mA		0.5	1	V
I_LKG(INH)	Sleep mode leakage current		INH = 0 V	–0.5		0.5	μA
R_PD	Pull-down resistance		Sleep Mode	2.5	4	6	MΩ
WAKE Input Characteristics
V_IH	High-level input voltage		Sleep mode	4			V
V_IL	Low-level input voltage		Sleep mode			2	V
I_IL	Low level input leakage current		WAKE = 1 V			3	μA
V_HYS	Input hysteresis			800		1200	mV
nRST Bidirectional Characteristics
V_IH	High level input voltage			0.8			V_CCOUT
V_IL	Low level input voltage					0.2	V_CCOUT
V_OL	Low level output voltage		I_O = 2 mA.			0.2	V_CCOUT
I_IH	High level input leakage current		nRST = V_CCOUT	-1		1	μA
R_PU	Pull-up resistance to V_CCOUT			160	240	320	k?
SDI Input Characteristics
V_IH	High level input voltage			0.8			V_CCOUT
V_IL	Low level input voltage					0.2	V_CCOUT
I_IH	High level input leakage current		SDI = V_CCOUT⁽²⁾	-1		1	μA
I_IL	Low level input leakage current		SDI = 0 V	-130		-50	μA
R_PU	Pull-up resistance			40	60	80	k?
I_LKG(OFF)	Unpowered leakage current		SDI = 5.5 V, V_SUP = 0 V	-1		1	μA
C_IN	Input capacitance		20 MHz	4		10	pF
SCLK Input Characteristics
V_IH	High level input voltage			0.7			V_CCOUT
V_IL	Low level input voltage					0.3	V_CCOUT
I_IH	High level input leakage current		SCLK = V_CCOUT⁽²⁾	50		130	μA
I_IL	Low level input leakage current		SCLK = 0 V	-1		1	μA
R_PD	Pull-down resistance			40	60	80	k?
I_LKG(OFF)	Unpowered leakage current		SCLK = 5.5 V, V_SUP = 0 V	-1		1	μA
C_IN	Input capacitance		20 MHz	4		10	pF
nCS Input Characteristics
V_IH	High level input voltage	High level input voltage	High level input voltage	0.7			V_CCOUT
V_IL	Low level input voltage	Low level input voltage	Low level input voltage			0.3	V_CCOUT
I_IH	High level input leakage current		nCS = V_CCOUT	-1		1	μA
I_IL	Low level input leakage current		nCS = 0 V	-130		-50	μA
R_PU	Pull-up resistor			40	60	80	k?
I_LKG(OFF)	Unpowered leakage current		nCS = 5.5 V, V_SUP = 0 V	-1		1	μA
C_IN	Input capacitance		20 MHz	4		10	pF
SDO Output Characteristics
V_OH	High-level output voltage		I_OH = -2 mA	0.8			V_CCOUT
V_OL	Low-level output voltage		I_OL = 2 mA			0.2	V_CCOUT
I_LKG(OFF)	Unpowered leakage current		V_nCS = 5.5 V	-1		1	μA

(1) Test according to ISO 11898-2:2003

(2) Note that there is an internal pull-up resistor to V_CCOUT. If externally driven to a higher or lower voltage, the pin leakage measurement will be increased.