ZHCSPG0 December 2021 TCAN1167-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 說明（續(xù)）
- 6 Pin Configurations and Functions
- 7 Specifications
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 VSUP Pin
- 9.3.2 VCCOUT Pin
- 9.3.3 Digital Inputs and Outputs
- 9.3.4 GND
- 9.3.5 INH Pin
- 9.3.6 WAKE Pin
- 9.3.7 nRST Pin
- 9.3.8 SDO
- 9.3.9 nCS Pin
- 9.3.10 SCLK
- 9.3.11 SDI
- 9.3.12 CAN Bus Pins
- 9.3.13 Local Faults
- 9.3.14 Watchdog
- 9.3.15 Bus Fault Detection and Communication
- 9.4 Device Functional Modes
- 9.5
Programming
- 9.5.1 Serial Peripheral Interface (SPI) Communication
- 9.5.2 Serial Clock Input (SCLK)
- 9.5.3 Serial Data Input (SDI)
- 9.5.4 Serial Data Output (SDO)
- 9.5.5 Chip Select Not (nCS)
- 9.5.6
Registers
- 9.5.6.1 DEVICE_ID_y Register (Address = 0h + formula) [reset = xxh]
- 9.5.6.2 REV_ID_MAJOR Register (Address = 8h) [reset = 00h]
- 9.5.6.3 REV_ID_MINOR Register (Address = 9h) [reset = 00h]
- 9.5.6.4 SPI_RSVD_x Register (Address = Ah + formula) [reset = 00h]
- 9.5.6.5 Scratch_Pad_SPI Register (Address = Fh) [reset = 00h]
- 9.5.6.6 MODE_CNTRL Register (Address = 10h) [reset = 04h]
- 9.5.6.7 WD_CONFIG_1 Register (Address = 13h) [reset = 54h]
- 9.5.6.8 WD_CONFIG_2 Register (Address = 14h) [reset = 02h]
- 9.5.6.9 WD_INPUT_TRIG Register (Address = 15h) [reset = 00h]
- 9.5.6.10 WD_QA_CONFIG Register (Address = 2Dh) [reset = 0h]
- 9.5.6.11 WD_QA_ANSWER Register (Address = 2Eh) [reset = 0h]
- 9.5.6.12 WD_QA_QUESTION Register (Address = 2Fh) [reset = 0h]
- 9.5.6.13 STATUS (address = 40h) [reset = 00h]
- 9.5.6.14 INT_GLOBAL Register (Address = 50h) [reset = 0h]
- 9.5.6.15 INT_1 Register (Address = 51h) [reset = 0h]
- 9.5.6.16 INT_2 Register (Address = 52h) [reset = 40h]
- 9.5.6.17 INT_3 Register (Address 53h) [reset = 0h]
- 9.5.6.18 INT_CANBUS Register (Address = 54h) [reset = 0h]
- 9.5.6.19 INT_ENABLE_1 Register (Address = 56h) [reset = F3h]
- 9.5.6.20 INT_ENABLE_2 Register (Address = 57h) [reset = 3Fh]
- 9.5.6.21 INT_ENABLE_3 Register (Address =58h) [reset = 80h]
- 9.5.6.22 INT_ENABLE_CANBUS Register (Address = 59h) [reset = 7Fh]
- 9.5.6.23 INT_RSVD_y Register (Address = 5Ah + formula) [reset = 00h]
- 10Application Information Disclaimer
- 11Power Supply Requirements
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- DMT|14
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- DMT|14
訂購信息
9.3.14.4.3 WD Question and Answer Value Generation
The 4-bit WD question, WD_QA_QUESTION[3:0], is generated by 4-bit Markov chain process. A Markov chain is a stochastic process with Markov property, which means that state changes are probabilistic, and the future state depends only on the current state. The valid and complete WD answer sequence for each WD Q&A mode is as follows:
- For WD Q&A multi-answer:
- Three correct SPI WD answers are received during RESPONSE WINDOW 1.
- One correct SPI WD answer is received during RESPONSE WINDOW 2.
- In addition to the previously listed timing, the sequence of four responses shall be correct.
The WD question value is latched in the WD_QUESTION[3:0] bits of the WD_QA_QUESTION register and can be read out at any time.
The Markov chain process is clocked by the 4-bit Question counter at the transition from b1111 to b0000. This includes the condition of a correct answer (correct answer value and correct timing response). The logic combination of the 4-bit questions WD_QUESTION [3:0] generation is given in Figure 9-6.
If the current y value is
0000, the next y value is 0001. The next watchdog question generation
process starts from that value.
Figure 9-6 Watchdog Question
GenerationTable 9-5 contains the answers for each question, as long as the question polynomial and answer generation configuration are both at their default values.
Table 9-5 Example answers to questions with default settings
| QUESTION IN WD_QUESTION_VALUE REGISTER | WD ANSWER BYTES (EACH BYTE TO BE WRITTEN INTO WD_QA_ANSWER REGISTER) | |||
|---|---|---|---|---|
| WD_ANSWER_RESP_3 | WD_ANSWER_RESP_2 | WD_ANSWER_RESP_1 | WD_ANSWER_RESP_0 | |
| WD_QUESTION | WD_ANSW_CNT 2'b11 | WD_ANSW_CNT 2'b10 | WD_ANSW_CNT 2'b01 | WD_ANSW_CNT 2'b00 |
| 0x0 | FF | 0F | F0 | 00 |
| 0x1 | B0 | 40 | BF | 4F |
| 0x2 | E9 | 19 | E6 | 16 |
| 0x3 | A6 | 56 | A9 | 59 |
| 0x4 | 75 | 85 | 7A | 8A |
| 0x5 | 3A | CA | 35 | C5 |
| 0x6 | 63 | 93 | 6C | 9C |
| 0x7 | 2C | DC | 23 | D3 |
| 0x8 | D2 | 22 | DD | 2D |
| 0x9 | 9D | 6D | 92 | 62 |
| 0xA | C4 | 34 | CB | 3B |
| 0xB | 8B | 7B | 84 | 74 |
| 0xC | 58 | A8 | 57 | A7 |
| 0xD | 17 | E7 | 18 | E8 |
| 0xE | 4E | BE | 41 | B1 |
| 0xF | 01 | F1 | 0E | FE |
Figure 9-7 WD Expected Answer
GenerationTable 9-6 Correct and Incorrect WD Q&A Sequence Run Scenarios for WD Q&A Multi-Answer Mode (WD_CFG = 0b)
| NUMBER OF WD ANSWERS | ACTION | WD STATUS BITS IN WD_QA_QUESTION REGISTER | COMMENTS | ||
|---|---|---|---|---|---|
| RESPONSE WINDOW 1 | RESPONSE WINDOW 2 | QA_ANSW_ERR | WD_ERR(1) | ||
| 0 answer | 0 answer | -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question | 0b | 1b | No answers |
| 0 answer | 4 INCORRECT answer | -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question | 1b | 1b | Total WD_ANSW_CNT[1:0] = 4 |
| 0 answer | 4 CORRECT answer | -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question | 0b | 1b | Total WD_ANSW_CNT[1:0] = 4 |
| 0 answer | 1 CORRECT answer | -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question | 0b | 1b | Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 CORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] < 4) |
| 1 CORRECT answer | 1 CORRECT answer | ||||
| 2 CORRECT answer | 1 CORRECT answer | ||||
| 0 answer | 1 INCORRECT answer | -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question | 1b | 1b | Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] < 4) |
| 1 CORRECT answer | 1 INCORRECT answer | ||||
| 2 CORRECT answer | 1 INCORRECT answer | ||||
| 0 answer | 4 CORRECT answer | -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question | 0b | 1b | Less than 3 CORRECT ANSWER in WIN1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] = 4) |
| 1 CORRECT answer | 3 CORRECT answer | ||||
| 2 CORRECT answer | 2 CORRECT answer | ||||
| 0 answer | 4 INCORRECT answer | -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question | 1b | 1b | Less than 3 CORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] = 4) |
| 1 CORRECT answer | 3 INCORRECT answer | ||||
| 2 CORRECT answer | 2 INCORRECT answer | ||||
| 0 answer | 3 CORRECT answer | -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question | 0b | 1b | Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] < 4) |
| 1 INCORRECT answer | 2 CORRECT answer | -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question | 1b | 1b | |
| 2 INCORRECT answer | 1 CORRECT answer | ||||
| 0 answer | 3 INCORRECT answer | -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question | 1b | 1b | Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] < 4) |
| 1 INCORRECT answer | 2 INCORRECT answer | ||||
| 2 INCORRECT answer | 1 INCORRECT answer | ||||
| 0 answer | 4 CORRECT answer | -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question | 0b | 1b | Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 CORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] = 4) |
| 1 INCORRECT answer | 3 CORRECT answer | 1b | 1b | ||
| 2 INCORRECT answer | 2 CORRECT answer | ||||
| 0 answer | 4 INCORRECT answer | -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question | 1b | 1b | Less than 3 INCORRECT ANSWER in RESPONSE WINDOW 1 and more than 1 INCORRECT ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] = 4) |
| 1 INCORRECT answer | 3 INCORRECT answer | ||||
| 2 INCORRECT answer | 2 INCORRECT answer | ||||
| 3 CORRECT answer | 0 answer | -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD Question | 0b | 1b | Less than 4 CORRECT ANSW in RESPONSE WINDOW 1 and more than 0 ANSWER in RESPONSE WINDOW 2 (Total WD_ANSW_CNT[1:0] < 4) |
| 2 CORRECT answer | 0 answer | 0b | 1b | ||
| 1 CORRECT answer | 0 answer | ||||
| 3 CORRECT answer | 1 CORRECT answer | -New WD cycle starts after the 4th WD answer -Decrement WD failure counter -New WD cycle starts with a new WD question | 0b | 0b | CORRECT SEQUENCE |
| 3 CORRECT answer | 1 INCORRECT answer | -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question | 1b | 1b | Total WD_ANSW_CNT[1:0] = 4 |
| 3 INCORRECT answer | 0 answer | -New WD cycle starts after the end of RESPONSE WINDOW 2 -Increment WD failure counter -New WD cycle starts with the same WD question | 1b | 1b | Total WD_ANSW_CNT[1:0] < 4 |
| 3 INCORRECT answer | 1 CORRECT answer | -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question | 1b | 1b | Total WD_ANSW_CNT[1:0] = 4 |
| 3 INCORRECT answer | 1 INCORRECT answer | -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question | 1b | 1b | Total WD_ANSW_CNT[1:0] = 4 |
| 4 CORRECT answer | Not applicable | -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question | 0b | 1b | |
| 3 CORRECT answer + 1 INCORRECT answer | Not applicable | -New WD cycle starts after the 4th WD answer -Increment WD failure counter -New WD cycle starts with the same WD question | 1b | 1b | 4 CORRECT or INCORRECT ANSWER in RESPONSE WINDOW 1 |
| 2 CORRECT answer + 2 INCORRECT answer | Not applicable | ||||
| 1 CORRECT answer + 3 INCORRECT answer | Not applicable | ||||