ZHCSPG0 December 2021 TCAN1167-Q1
PRODUCTION DATA
INT_ENABLE_3 is shown in Figure 9-45 and described in Table 9-38.
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Interrupt mask for INT_3
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SPIERR_ENABLE | RSVD | ||||||
| R/W-1b | R-00h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | SPIERR_ENABLE | R/W | 1b | SPI error interrupt enable |
| 6-0 | RSVD | R | 00h | Reserved |