SLVSLJ5 March 2026 TCA9846
ADVANCE INFORMATION
The last bit of the target address defines the operation (read or write) to be performed. When it is high (1), a read is selected, while a low (0) selects a write operation.
Table 7-1 shows the TCA9846 address reference.
| INPUTS | I2C BUS TARGETADDRESS | |
|---|---|---|
| A1 | A0 | |
| L | SCL | 0xE0h (hexadecimal) |
| L | L | 0xE2h (hexadecimal) |
| L | SDA | 0xE4h (hexadecimal) |
| L: | H | 0xE6h (hexadecimal) |
| H | SCL | 0xE8h (hexadecimal) |
| H | L | 0xEAh (hexadecimal) |
| H | SDA | 0xECh (hexadecimal) |
| H | H | 0xEEh (hexadecimal) |
| SCL | SCL | 0xB0h (hexadecimal) |
| SCL | L | 0xB2h (hexadecimal) |
| SCL | SDA | 0xB4h (hexadecimal) |
| SCL | H | 0xB6h (hexadecimal) |
| SDA | SCL | 0xB8h (hexadecimal) |
| SDA | L | 0xBAh (hexadecimal) |
| SDA | SDA | 0xBCh (hexadecimal) |
| SDA | 1 | 0xBEh (hexadecimal) |