ZHCSC52D January 2014 – November 2019 TCA9545A
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, TCA9545A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.
A power-on reset is shown in Figure 20.
Figure 20. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC Table 3 specifies the performance of the power-on reset feature for TCA9545A for both types of power-on reset.
Table 3. Recommended Supply Sequencing And Ramp Rates(1)
| PARAMETER | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|
| VCC_FT | Fall time | See Figure 20 | 1 | 100 | ms | |
| VCC_RT | Rise time | See Figure 20 | 0.1 | 100 | ms | |
| VCC_TRR | Time to re-ramp (when VCC drops below VPORF(min) – 50 mV or when VCC drops to GND) | See Figure 20 | 40 | μs | ||
| VCC_GH | Level that VCC can glitch down to, but not cause a functional disruption when VCC_GW = 1 μs | See Figure 21 | 1.2 | V | ||
| VCC_GW | Glitch width that will not cause a functional disruption when VCC_GH = 0.5 × VCC | See Figure 21 | 10 | μs | ||
| VPORF | Voltage trip point of POR on falling VCC | See Figure 22 | 0.8 | 1.25 | V | |
| VPORR | Voltage trip point of POR on rising VCC | See Figure 22 | 1.05 | 1.5 | V | |
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 21 and Table 3 provide more information on how to measure these specifications.
Figure 21. Glitch Width and Glitch Height VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 22 and Table 3 provide more details on this specification.
Figure 22. VPOR