ZHCSB75E May 2013 – June 2016 TAS5729MD
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 描述
- 4 修訂歷史記錄
- 5 Related Devices
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Digital I/O Pins
- 7.6 Master Clock
- 7.7 Serial Audio Port
- 7.8 Protection Circuitry
- 7.9 Speaker Amplifier in All Modes
- 7.10 Speaker Amplifier in Stereo Bridge Tied Load (BTL) Mode
- 7.11 Speaker Amplifier in Stereo Post-Filter Parallel Bridge Tied Load (Post-Filter PBTL) Mode
- 7.12 Headphone Amplifier and Line Driver
- 7.13 Reset Timing
- 7.14 I2C Control Port
- 7.15 Typical Electrical Power Consumption
- 7.16 Typical Characteristics
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3 Feature Description
- 9.4 Device Functional Modes
- 9.5 Programming
- 9.6
Register Maps
- 9.6.1 Clock Control Register (0x00)
- 9.6.2 Device ID Register (0x01)
- 9.6.3 Error Status Register (0x02)
- 9.6.4 System Control Register 1 (0x03)
- 9.6.5 Serial Data Interface Register (0x04)
- 9.6.6 System Control Register 2 (0x05)
- 9.6.7 Soft Mute Register (0x06)
- 9.6.8 Volume Registers (0x07, 0x08, 0x09)
- 9.6.9 Volume Configuration Register (0x0E)
- 9.6.10 Modulation Limit Register (0x10)
- 9.6.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
- 9.6.12 PWM Shutdown Group Register (0x19)
- 9.6.13 Start/Stop Period Register (0x1A)
- 9.6.14 Oscillator Trim Register (0x1B)
- 9.6.15 BKND_ERR Register (0x1C)
- 9.6.16 Input Multiplexer Register (0x20)
- 9.6.17 Channel 4 Source Select Register (0x21)
- 9.6.18 PWM Output MUX Register (0x25)
- 9.6.19 AGL Control Register (0x46)
- 9.6.20 PWM Switching Rate Control Register (0x4F)
- 9.6.21 EQ Control (0x50)
-
10Application and Implementation
- 10.1 Application Information
- 10.2
Typical Applications
- 10.2.1 Stereo BTL Configuration With Headphone and Line Driver Amplifier
- 10.2.2 Mono PBTL Configuration with Headphone and Line Driver Amplifier
- 11Power Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機械、封裝和可訂購信息
6 Pin Configuration and Functions
DCA Package
48-Pin HTSSOP With PowerPAD™
Top View
Pin Functions
| PIN | TYPE(1) | TERMINATION | DESCRIPTION | |
|---|---|---|---|---|
| NAME | NUMBER | |||
| ADR/SPK_FAULT | 20 | DI/DO | — | Dual-function pin which sets the LSB of the 7-bit I2C address to 0 if pulled to GND, 1 if pulled to DVDD. If configured to be a fault output via the System Control Register 2 (0x05), this pin is pulled low when an internal fault with the speaker amplifier occurs. A pullup or pulldown resistor is required, as is shown in the Typical Applications. |
| AGND | 36 | P | — | Ground for analog circuitry(3) |
| AVDD | 19 | P | — | Power supply for internal analog circuitry |
| ANA_REG1 | 18 | P | — | Linear voltage regulator output derived from AVDD supply which is used for internal analog circuitry. Nominal 1.8-V output.(2) |
| ANA_REG2 | 37 | P | — | Linear voltage regulator output derived from AVDD supply which is used for internal analog circuitry. Nominal 3.3-V output.(2) |
| BSTRPx | 3, 42, 46, 47 | P | — | Connection points for the bootstrap capacitors which are used to create a power supply for the high-side gate drive of the device. |
| DGND | 35 | P | — | Ground for digital circuitry(3) |
| DIG_REG | 24 | P | — | Linear voltage regulator output derived from the DVDD supply which is used for internal digital circuitry.(2) |
| DR_CN | 12 | P | — | Negative pin for capacitor connection used in headphone amplifier and line driver charge pump |
| DR_CP | 13 | P | — | Positive pin for capacitor connection used in headphone amplifier and line driver charge pump |
| DR_INx | 7, 10 | AI | — | Input for channel A or B of headphone amplifier or line driver |
| DR_OUTx | 8, 9 | AO | — | Output for channel A or B of headphone amplifier or line driver |
| DR_SDI | 39 | DI | — | Places the headphone amplifier/line driver in shutdown when pulled low. |
| DRVSS | 11 | P | — | Negative supply generated by charge pump for ground centered headphone and line driver output |
| DRVDD | 14 | P | — | Power supply for internal headphone and line driver circuitry |
| DVDD | 34 | P | — | Power supply for the internal digital circuitry |
| GVDD_REG | 40 | P | — | Voltage regulator derived from PVDD supply(2) |
| LRCLK | 26 | DI | Pulldown | Word select clock of the serial audio port. |
| MCLK | 21 | DI | Pulldown | Master clock used for internal clock tree and sub-circuit and state machine clocking |
| NC | 31 | — | — | Not connected inside the device (all NC terminals should be connected to ground for optimal thermal performance) |
| OSC_GND | 23 | P | — | Ground for oscillator circuitry (this terminal should be connected to the system ground) |
| OSC_RES | 22 | AO | — | Connection point for oscillator trim resistor |
| PDN | 25 | DI | Pullup | Quick powerdown of the device that is used upon an unexpected loss of the PVDD or DVDD power supply to quickly transition the outputs of the speaker amplifier to Hi-Z. This quick powerdown feature avoids the audible anamolies that would occur as a result of loss of either of the supplies. |
| PGND | 1, 44 | P | — | Ground for power device circuitry(3) |
| PLL_FLTM | 16 | AI/AO | — | Negative connection point for the PLL loop filter components |
| PLL_FLTP | 17 | AI/AO | — | Positive connection point for the PLL loop filter components |
| PLL_GND | 15 | P | — | Ground for PLL circuitry (this terminal should be connected to the system ground) |
| PowerPAD™ | — | P | — | Thermal and ground pad that provides both an electrical connection to the ground plane and a thermal path to the PCB for heat dissipation. This pad must be grounded to the system ground. (3) |
| PVDD | 4, 41 | P | — | Power supply for internal power circuitry |
| RST | 32 | DI | Pullup | Places the device in reset when pulled low |
| SCL | 30 | DI | — | I2C serial control port clock |
| SCLK | 27 | DI | Pulldown | Bit clock of the serial audio port |
| SDA | 29 | DI/DO | — | I2C serial control port data |
| SDIN | 28 | DI | Pulldown | Data line to the serial data port |
| SPK_OUTx | 2, 43, 45, 48 | AO | — | Speaker amplifier outputs |
| SSTIMER | 38 | AI | — | Controls ramp time of SPK_OUTx to minimize pop. Leave this pin floating for BD mode. Requires capacitor to GND in AD mode, as is shown in Typical Applications. The capacitor determines the ramp time. |
| TEST1 | 5 | DO | — | Used for testing during device production (this terminal must be left floating) |
| TEST2 | 6 | DO | — | Used for testing during device production (this terminal must be left floating) |
| TEST3 | 33 | DI | — | Used for testing during device production (this terminal must be connected to GND) |
(1) TYPE: AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, P = Power, G = Ground (0 V)
(2) This pin is provided as a connection point for filtering capacitors for this supply and must not be used to power any external circuitry.
(3) This pin should be connected to the system ground.