9.3.1 Power Supply

To facilitate system design, the TAS5729MD requires only a single low-voltage DVDD supply in addition to the higher-voltage PVDD power supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a floating voltage supply (for example, the high-side gate drive) is accommodated by built-in bootstrap circuitry requiring only a few external capacitors.

To provide good electrical and acoustical characteristics, the PWM signal path for the output stage is designed as identical, independent half-bridges that operate in pairs to produce the full-bridge outputs capable of driving BTL loads. For this reason, each half-bridge has separate bootstrap pins (BSTRPx) and power-stage supply pins (PVDD). The gate drive voltage (GVDD_REG) is derived from the PVDD voltage. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power-supply pins and decoupling capacitors must be avoided.

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BSTRPx) to the power-stage output pin (SPK_OUTx). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive regulator output pin (GVDD_REG) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver.

Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each pair of half-bridges has independent power-stage supply pins (PVDD). For optimal electrical performance, EMI compliance, and system reliability, each PVDD pin must be decoupled with a ceramic capacitor placed as close as possible to each supply pin, as shown in Typical Applications.

9.3.2 ADR/SPK_FAULT

The ADR/SPK_FAULT pin is an input pin during power-up, and can be pulled high or low through a pullup or pulldown resistor, as shown in Typical Applications. High sets an I²C address of 101011[^R/_W], and low sets an address of 101010[^R/_W]. Additionally, via the control port, the ADR/SPK_FAULT pin can be configured to serve as the fault indicator for the speaker amplifier.

9.3.3 Device Protection System

9.3.4 Clock, Auto Detection, and PLL

The TAS5729MD is an I²S slave device that requires a valid master clock (MCLK), bit clock (SCLK), and word clock (LRCLK) to play audio. The digital audio processor (DAP) supports all of the sample rates and MCLK rates that are defined in the Clock Control Register (0x00). The TAS5729MD checks to verify that SCLK is a specific value of 32 × f_S, 48 × f_S, or 64 × f_S. The DAP only supports a 1 × f_S LRCLK.

The device has robust clock error handling that uses a built-in auto detect block to quickly detect changes or errors. When the system detects a clock change or error, it mutes the audio (through a single-step mute) and forces PLL to limp, where output PWMs continue to switch in idle but the device cannot play audio. Once the clocks are valid and stable, the system auto detects the new rate and reverts to normal operation. During this process, the volume is restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back slowly (also called soft unmute) as defined in volume register (0x0E).

Table 1 shows the valid MCLK rates across different f_S rates. For 44.1-kHz or 48-kHz f_S rates, a 64 × f_S MCLK rate is supported. If a 64 × f_S SCLK rate is used, a common 64 × f_S clock can be used for both MCLK and SCLK.

9.3.5 Serial Data Interface

Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5729MD DAP accepts serial data in 16-, 20-, or 24-bit left-justified, right-justified, or I²S serial data format.

9.3.6 PWM Section

The TAS5729MD DAP device uses noise-shaping and sophisticated nonlinear correction algorithms to achieve high-power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP and outputs two BTL PWM audio output channels.

The PWM section has internal dc-blocking filters that can be enabled and disabled using the System Control Register 1 (0x03). The controls for the dc-blocking filters are ganged together and enabling or disabling will affect both channels simultaneously. The filter cutoff frequency is less than 1 Hz. Individual-channel de-emphasis filters for 44.1 kHz and 48 kHz are included and can be enabled and disabled.

Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.

9.3.7 I²C Compatible Serial Control Interface

The TAS5729MD DAP has an I²C serial control slave interface to receive commands from a system controller. The serial control interface supports both normal-speed (100 kHz) and high-speed (400 kHz) operations without wait states. As an added feature, this interface operates even if MCLK is absent.

The serial control interface supports both single-byte and multiple-byte read and write operations for status registers and the general control registers associated with the PWM.

9.3.8 Serial Interface Control And Timing

9.3.8.1 I²S Timing

I²S timing uses LRCLK to define when the data being transmitted is for the left channel and when the data is for the right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or 64 × f_S is used to clock in the data. A delay of one bit clock exists from the time the LRCLK signal changes state to the first bit of data on the data lines. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP masks unused trailing data-bit positions.

NOTE:

All data presented in 2s-complement form with MSB first.

Figure 32. I²S 64 × f_S Format

NOTE:

All data presented in 2s-complement form with MSB first.

Figure 33. I²S 48 × f_S Format

NOTE:

All data presented in 2s-complement form with MSB first.

Figure 34. I²S 32 × f_S Format

9.3.8.2 Left-Justified

Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when the data is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × f_S is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB-first and is valid on the rising edge of the bit clock. The DAP masks unused trailing data-bit positions.

NOTE:

All data presented in 2s-complement form with MSB first.

Figure 35. Left-Justified 64 × f_S Format

NOTE:

All data presented in 2s-complement form with MSB first.

Figure 36. Left-Justified 48 × f_S Format

NOTE:

All data presented in 2s-complement form with MSB first.

Figure 37. Left-Justified 32 × f_S Format

9.3.8.3 Right-Justified

Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when the data is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × f_S is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before LRCLK transitions. The data is written MSB-first and is valid on the rising edge of bit clock. The DAP masks unused leading data-bit positions.

Figure 38. Right-Justified 64 × f_S Format

Figure 39. Right-Justified 48 × f_S Format

Figure 40. Right-Justified 32 × f_S Format

9.3.9 Automatic Gain Limiting (AGL)

The AGL scheme has two AGL blocks. The high-band left/right channels have one ganged AGL and the low-band left/right channels have the other AGL.

The AGL input/output diagram is shown in Figure 41.

Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
 • Each AGL has adjustable threshold levels.
 • Programmable attack and release rate
 • Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,
    and decay times can be set slow enough to avoid pumping.

Figure 41. Automatic Gain Limiting

T = 9.23 format, all other AGL coefficients are 3.23 format

Figure 42. AGL Structure

9.3.10 PWM Level Meter

The structure in Figure 43 shows the PWM level meter that can be used to study the power profile.

Figure 43. PWM Level Meter Structure

9.4.1 Device Protection Mode

The TAS5729MD contains a complete set of protection circuits carefully designed to make system design efficient as well as to protect the device against any kind of permanent failures due to overcurrent, overtemperature, and undervoltage. Any of these errors are reported in the ERROR STATUS register, and a fault error signal can be monitored on the SPK_FAULT pin if configured in the system control register. If any of the protection circuits is activated, all half-bridge outputs are immediately set in the high-impedance (hi-Z) state.

9.4.2 Speaker Amplifier Mode

The TAS5729MD can be configured in different amplifier configurations:

• Stereo BTL mode
• Monaural PBTL mode

9.4.2.1 Stereo Mode

The classic stereo mode of operation uses the TAS5729MD device to amplify two independent signals that represent the left and right portions of a stereo signal. These amplified left and right audio signals are presented on differential output pairs shown as SPK_OUTA and SPK_OUTB for channel 1 and SPK_OUTC and SPK_OUTD for channel 2. The routing of the audio data that is presented on the SPK_OUTx outputs can be changed according to the PWM Output Mux Register (0x25). By default, the TAS5729MD device is configured to output channel 1 to the SPK_OUTA and SPK_OUTB outputs, and channel 2 to the SPK_OUTC and SPK_OUTD outputs. Stereo mode operation outputs are shown in Figure 44.

Figure 44. Stereo BTL Mode

9.4.2.2 Monaural Mode

When this mode of operation is used, the two stereo outputs of the device are placed in parallel, one with another to increase the power sourcing capabilities of the device. On the output side of the TAS5729MD device, the merging of the two output channels is done after the inductor portion of the output filter. Doing so requires two additional inductors, but allows smaller, less expensive inductors to be used because the current is divided between the two inductors. This process is called post-filter PBTL, and the monaural operation is shown in Figure 45.

Figure 45. Post-Filter PBTL

On the input side of the TAS5729MD device, the input signal to the monaural amplifier can be selected from a mix, left, or right frame from an I²S, LJ, or RJ signal. The routing of the audio data which is presented on the SPK_OUTx outputs must be configured with the PWM Output Mux Register (0x25).

9.4.3 Headphone/Line Amplifier

An integrated ground centered DirectPath combination headphone amplifier and line driver is integrated in the TAS5729MD. This headphone/line amplifier can be used independently from the device speaker amplifier modes, with analog single-ended inputs DR_INA and DR_INB, linked to the respective analog outputs DR_OUTA, and DR_OUTB. A basic diagram of the headphone/line amplifier is shown in Figure 46.

Figure 46. Headphone/Line Amplifier

The DR_SDI pin can be used to turn on or off the headphone amplifier and line driver. The DirectPath amplifier makes use of the provided positive and negative supply rails generated by the IC. The output voltages are centered at zero volts with the capability to swing to the positive rail or negative rail; combining this capability with the built-in click and pop reduction circuit, the DirectPath amplifier requires no output dc blocking capacitors.

9.5.1 I²C Serial Control Interface

The TAS5729MD DAP has a bidirectional I²C interface that is compatible with the I²C bus protocol and supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations. The DAP is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The control interface is used to program the registers of the device and to read device status.

The DAP supports the standard-mode I²C bus operation (100 kHz maximum) and the fast I²C bus operation (400 kHz maximum). The DAP performs all I²C operations without I²C wait cycles.

9.5.1.1 General I²C Operation

The I²C bus employs two signals: SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte (8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit.

Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is high to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 47.

The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The TAS5729MD holds SDA low during the acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the high level for the bus.

Figure 47. Typical I²C Sequence

An unlimited number of bytes can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 47.

9.5.1.3 Single-Byte Write

As shown in Figure 48, a single-byte data-write transfer begins with the master device transmitting a start condition followed by the I²C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a data-write transfer, the read/write bit is 0. After receiving the correct I²C device address and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or bytes corresponding to the TAS5729MD internal memory address being accessed. After receiving the address byte, the TAS5729MD again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5729MD again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.

Figure 48. Single-Byte Write Transfer

9.5.1.4 Multiple-Byte Write

A multiple-byte data-write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the DAP as shown in Figure 49. After receiving each data byte, the TAS5729MD responds with an acknowledge bit.

Figure 49. Multiple-Byte Write Transfer

9.5.1.5 Single-Byte Read

As shown in Figure 50, a single-byte data-read transfer begins with the master device transmitting a start condition followed by the I²C device address and the read/write bit. For the data-read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5729MD address and the read/write bit, TAS5729MD responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the TAS5729MD address and the read/write bit again. This time the read/write bit becomes a 1, indicating a read transfer. After receiving the address and the read/write bit, the TAS5729MD again responds with an acknowledge bit. Next, the TAS5729MD transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data-read transfer.

Figure 50. Single-Byte Read Transfer

9.5.1.6 Multiple-Byte Read

A multiple-byte data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are transmitted by the TAS5729MD to the master device as shown in Figure 51. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte.

Figure 51. Multiple-Byte Read Transfer

9.5.2 26-Bit 3.23 Number Format

All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. A number formatted as a 3.23 number means that the binary point has three bits to the left and 23 bits to the right. This configuration is shown in Figure 52.

Figure 52. 3.23 Format

The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 52. If the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must be inverted, a 1 added to the result, and then the weighting shown in Figure 53 applied to obtain the magnitude of the negative number.

Figure 53. Conversion Weighting Factors—3.23 Format to Floating Point

Gain coefficients, entered via the I²C bus, must be entered as 32-bit binary numbers. The format of the 32-bit number (4-byte or 8-digit hexadecimal number) is shown in Figure 54.

Figure 54. Alignment of 3.23 Coefficient in 32-Bit I²C Word

Table 4. Serial Control Interface Register Summary

9.6.1 Clock Control Register (0x00)

The clocks and data rates are automatically determined by the TAS5729MD. The clock control register contains the autodetected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency.

9.6.2 Device ID Register (0x01)

The device ID register contains the ID code for the firmware revision.

9.6.3 Error Status Register (0x02)

The error bits are sticky and are not cleared by the hardware, which means that the software must clear the register (write zeroes) and then read them to determine if they are persistent errors.

Error definitions:

• MCLK error: MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
• SCLK error: The number of SCLKs per LRCLK is changing.
• LRCLK error: LRCLK frequency is changing.
• Frame slip: LRCLK phase is drifting with respect to internal frame sync.

9.6.4 System Control Register 1 (0x03)

System control register 1 has several functions:

9.6.5 Serial Data Interface Register (0x04)

As shown in Table 9, the TAS5729MD supports nine serial data modes. The default is 24-bit, I²S mode.

9.6.6 System Control Register 2 (0x05)

When bit D6 is set low, the system exits all-channel shutdown and starts playing audio; otherwise, the outputs are shutdown (hard mute).

9.6.7 Soft Mute Register (0x06)

Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute).

9.6.8 Volume Registers (0x07, 0x08, 0x09)

Step size is 0.125 dB and volume registers are 2 bytes.

Volume Range: +24dB to –103.75dB

Step-Size: 0.125dB

Formula:

Target Volume Level (dB) = 'V'

• Step-1: Calculate (24 – V)/0.125
• Step-2: Convert calculated decimal value to 2-byte hexadecimal to get the register hex-value

Examples:

Target Volume = 12dB

• (24 – 12)/0.125 = 96
• Converting decimal value 96 to 2-byte hexadecimal gives x0060

Target Volume = 0dB

• (24 – 0)/0.125 = 192
• Converting decimal value 192 to 2-byte hexadecimal gives x00C0

Target Volume = –12dB

• (24 – (–12))/0.125 = 36/0.125 = 288
• Converting decimal value 288 to 2-byte hexadecimal gives x0120

9.6.9 Volume Configuration Register (0x0E)

9.6.10 Modulation Limit Register (0x10)

9.6.11 Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)

Internal PWM channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14.

ICD settings have high impact on audio performance (for example, dynamic range, THD, crosstalk, and so on). Therefore, appropriate ICD settings must be used. By default, the device has ICD settings for the AD mode. If used in BD mode, then update these registers before coming out of all-channel shutdown.

9.6.12 PWM Shutdown Group Register (0x19)

Settings of this register determine which PWM channels are active. The value should be 0x30 for BTL mode and 0x3A for post-filter PBTL mode. The default value of this register is 0x30. The functionality of this register is tied to the state of bit D5 in the system control register.

This register defines which channels belong to the shutdown group (SDG). If a 1 is set in the shutdown group register, that particular channel is not started following an exit out of all-channel shutdown command (if bit D5 is set to 0 in system control register 2, 0x05).

9.6.13 Start/Stop Period Register (0x1A)

This register is used to control the soft-start and soft-stop period following an enter or exit all-channel shutdown command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown. The times are only approximate and vary depending on device activity level and I²S clock stability.

9.6.14 Oscillator Trim Register (0x1B)

The TAS5729MD PWM processor contains an internal oscillator to support autodetect of the I²S clock rates. This reduces system cost because an external reference is not required. Currently, TI recommends a reference resistor value of 18.2 kΩ (1%). This should be connected between OSC_RES and DVSSO.

Writing 0x00 to register 0x1B enables the trim that was programmed at the factory.

Note that trim must always be run following reset of the device.

9.6.15 BKND_ERR Register (0x1C)

When a back-end error signal is received from the internal power stage, the power stage is reset, stopping all PWM activity. Subsequently, the modulator waits approximately for the time listed in Table 18 before attempting to re-start the power stage.

9.6.16 Input Multiplexer Register (0x20)

This register controls the modulation scheme (AD or BD mode) as well as the routing of I²S audio to the internal channels.

9.6.17 Channel 4 Source Select Register (0x21)

This register selects the channel 4 source.

9.6.18 PWM Output MUX Register (0x25)

This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be output to any external output pin.

Note that channels are encoded so that channel 1 = 0x00, channel 2 = 0x01, …, channel 4 = 0x03.

9.6.19 AGL Control Register (0x46)

9.6.20 PWM Switching Rate Control Register (0x4F)

The output PWM switching frequency is configurable as a multiple of the input sample rate (f_S). The PWM frequency can be set to one of 6 × f_S, 7 × f_S, 8 × f_S, or 9 × f_S. PWM switching rate should be selected through the register 0x4F before coming out of all-channel shutdown.

9.6.21 EQ Control (0x50)