ZHCSC43B January 2014 – April 2015 TAS2552
PRODUCTION DATA.

| TERMINAL | INPUT/OUTPUT/POWER | DESCRIPTION | |
|---|---|---|---|
| NAME | BALL WCSP | ||
| PGND | A1 | P | Power ground. Connect to high current ground plane. |
| OUT– | A2 | O | Inverting Class D output. |
| OUT+ | A3 | O | Non-inverting Class D output. |
| PVDD | A4 | P | Class-D power supply. Connected internally to VBOOST – do not drive this terminal externally. |
| VBOOST | A5 | P | 8.5 V boost output. Connected internally to PVDD – do not drive this terminal externally. |
| BIAS | B1 | O | Mid-rail reference for Class D channel. |
| VSENSE– | B2 | I | Inverting voltage sense input. |
| VSENSE+ | B3 | I | Non-inverting voltage sense input. |
| SW | B4,B5 | I/O | Boost switch terminal. |
| AGND | C1,C2 | P | Analog ground. Connect to low noise ground plane. |
| VREG | C3 | O | High-side FET gate drive boost converter. |
| PGND | C4,C5 | P | Power ground. Connect to high current ground plane. |
| VBAT | D1 | P | Battery power supply. Connect to 3.0 V to 5.5 V battery supply. |
| AIN– | D2 | I | Inverting analog input. |
| DIN | D3 | I | Audio serial data input. Format is I2S, LJF, RJF, or TDM data. |
| ADDR | D4 | I | I2C address select terminal. Set ADDR = GND for device 7-bit address 0x40; set ADDR = IOVDD for 7-bit address 0x41. |
| SDA | D5 | I/O | I2C control bus data. |
| AVDD | E1 | P | Analog low voltage supply terminal. Connect to 1.65 V to 1.95 V supply. |
| AIN+ | E2 | I | Non-inverting analog input. |
| DOUT | E3 | O | Serial I/V digital output. Format is I2S, LJF, RJF, TDM, or undecimated PDM data. |
| IVCLKIN | E4 | I | Serial clock input for undecimated PDM I/V data. |
| SCL | E5 | I | I2C control bus clock. |
| EN(1) | F2 | I | Device enable (HIGH = Normal Operation, LOW = Standby) |
| WCLK | F3 | I | Audio serial word clock. |
| BCLK | F4 | I | Audio serial bit clock. |
| MCLK | F5 | I | External master clock. |
| IOVDD | F1 | P | Supply for digital input and output levels. Voltage range is 1.5 V to 3.6 V. |