ZHCSKM5 December 2019 TAS2110
PRODUCTION DATA.
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | QFN | ||
| AD0 | 19 | I | I2C address pin LSB. |
| AD1 | 12 | I | I2C address pin LSB+1. |
| BGND | 14 | P | Boost ground. Connect to PCB GND plane. |
| DREG | 2 | P | Digital core voltage regulator output. Bypass to GND with a cap. Do not connect to external load. |
| FSYNC | 5 | IO | I2S word clock or TDM frame sync. |
| GREG | 13 | P | High-side gate CP regulator output. Do not connect to external load. |
| GND | 28 | P | Digital ground. Connect to PCB GDN plane. |
| IRQZ | 18 | O | Open drain, active low interrupt pin. Pull up to VDDD with resistor if optional internal pull up is not used. |
| GPIO | 22 | IO | General purpose input/output, no connect if not used. |
| NC | 1 | - | No Connect. Can float or connect to any support or signal. |
| 8 | |||
| 9 | |||
| 17 | |||
| 23 | |||
| 24 | |||
| 32 | |||
| NC2 | 20 | - | No Connect. Can float or connect to ground. Do not connect to other signals or supplies. |
| 29 | |||
| OUT_N | 26 | O | Class-D negative output for receiver channel. |
| OUT_P | 21 | O | Class-D positive output for receiver channel. |
| PGND | 27 | P | Power stage ground. Connect to PCB GND plane. |
| PVDD | 25 | P | Power stage supply. |
| SBCLK | 6 | IO | I2S/TDM serial bit clock. |
| SCL | 4 | I | I2C Clock Pin. Pull up to VDD with a resistor. |
| SDA | 3 | IO | I2C Data Pin. Pull up to VDD with a resistor. |
| SDIN | 11 | I | I2S/TDM serial data input. |
| SDOUT | 10 | IO | I2S/TDM serial data output. |
| SDZ | 7 | I | Active low hardware shutdown. |
| SW | 15 | P | Boost converter switch input. |
| VBAT | 30 | P | Battery power supply input. Connect to 2.7 V to 5.5 V supply and decouple with a cap. |
| VBST | 16 | P | Boost converter output. Do not connect to external load. |
| VDD | 31 | P | Analog, digital, and IO power supply. Connect to 1.8 V supply and decouple to GND with cap. |