ZHCSKM5 December 2019 TAS2110
PRODUCTION DATA.
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| tH(SBCLK) | SBCLK high period | 20 | ns | |||
| tL(SBCLK) | SBCLK low period | 20 | ns | |||
| tSU(FSYNC) | FSYNC setup time | 8 | ns | |||
| tHLD(FSYNC) | FSYNC hold time | 8 | ns | |||
| tSU(FSYNC) | SDIN setup time | 8 | ns | |||
| tHLD(SDIN) | SDIN hold time | 8 | ns | |||
| td(DO-SBCLK) | SBCLK to SDOUT delay | 50% of FSYNC to 50% of SDOUT | 21 | ns | ||
| tr(SBCLK) | SBCLK rise time | 10% - 90 % Rise Time | 8 | ns | ||
| tf(SBCLK) | SBCLK fall time | 90% - 10 % Fall Time | 8 | ns | ||
Figure 1. I2C Timing Diagram
Figure 2. TDM Timing Diagram