As with any high-speed design, there are many
factors which influence the overall performance.
The following list indicates critical areas for
consideration during design:
- Use 85 Ω impedance traces when interfacing with
PCIe CEM connectors. Length matching on the P and
N traces should be done on the single-ended
segments of the differential pair.
- Use a uniform trace width and trace spacing for
differential pairs.
- Place AC-coupling capacitors near to the receiver
end of each channel segment to minimize
reflections.
- For Gen 3.0, 4.0, and 5.0, AC-coupling capacitors
of 220 nF are recommended, set the maximum body
size to 0402, and add a cutout void on the GND
plane below the landing pad of the capacitor to
reduce parasitic capacitance to GND.
- Back-drill connector vias and signal vias to
minimize stub length.
- Use reference plane vias to ensure a low
inductance path for the return current.