ZHCSTI9D October 1990 – October 2023 SN65175 , SN75175
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Figure 4-1 D, N, or NS Package (Top
View)| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| 1B | 1 | I | Channel 1 Differential Receiver Inverting Input |
| 1A | 2 | I | Channel 1 Differential Receiver Non-Inverting Input |
| 1Y | 3 | O | Channel 1 Single Ended Output |
| 1,2EN | 4 | I | Active High Enable for Channels 1 and 2 |
| 2Y | 5 | O | Channel 2 Single Ended Output |
| 2A | 6 | I | Channel 2 Differential Receiver Non-Inverting Input |
| 2B | 7 | I | Channel 2 Differential Receiver Inverting Input |
| GND | 8 | GND | Device GND |
| 3B | 9 | I | Channel 3 Differential Receiver Inverting Input |
| 3A | 10 | I | Channel 3 Differential Receiver Non-Inverting Input |
| 3Y | 11 | O | Channel 3 Single Ended Output |
| 3,4EN | 12 | I | Active High Enable for Channels 3 and 4 |
| 4Y | 13 | O | Channel 4 Single Ended Output |
| 4A | 14 | I | Channel 4 Differential Receiver Non-Inverting Input |
| 4B | 15 | I | Channel 4 Differential Receiver Inverting Input |
| VCC | 16 | PWR | Device VCC (4.75 V to 5.25 V) |