SCES593F JULY 2004 – July 2017 SN74AUP1G80
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics: TA = 25°C
- 6.6 Electrical Characteristics: TA = -40°C to +85°C
- 6.7 Timing Requirements
- 6.8 Switching Characteristics: CL = 5 pF
- 6.9 Switching Characteristics: CL = 10 pF
- 6.10 Switching Characteristics: CL = 15 pF
- 6.11 Switching Characteristics: CL = 30 pF
- 6.12 Operating Characteristics
- 6.13 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
訂購信息
1 Features
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II) - 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model
- Available in the Texas Instruments NanoStar™ Package
- Low Static-Power Consumption
(ICC = 0.9 µA Maximum) - Low Dynamic-Power Consumption
(Cpd = 4.3 pF Typical at 3.3 V) - Low Input Capacitance (Ci = 1.5 pF Typical)
- Low Noise – Overshoot and Undershoot <10% of VCC
- Ioff Supports Partial-Power-Down Mode Operation
- Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input
(Vhys = 250 mV Typical at 3.3 V) - Wide Operating VCC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- tpd = 4.4 ns Maximum at 3.3 V
- Suitable for Point-to-Point Applications
2 Applications
- Home Automation
- Factory Automation
- Test and Measurement
- Enterprise Switching
- Telecom Infrastructure
- Personal Electronics
- White Goods
3 Description
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family assures a low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see AUP – The Lowest-Power Family). This product also maintains excellent signal integrity (see Excellent Signal Integrity).
This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| SN74AUP1G80DBV | SOT-23 (5) | 1.60 mm × 2.90 mm |
| SN74AUP1G80DCK | SC70 (5) | 1.25 mm × 2.00 mm |
| SN74AUP1G80DRY | SON (6) | 1.00 mm × 1.45 mm |
| SN74AUP1G80DSF | SON (6) | 1.00 mm × 1.00 mm |
| SN74AUP1G80YFP | DSBGA (6) | 0.76 mm × 1.16 mm |
| SN74AUP1G80YZP | DSBGA (5) | 0.89 mm × 1.39 mm |
| SN74AUP1G80DPW | X2SON (5) | 0.80 mm × 0.80 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
Logic Diagram (Positive Logic)
