SCES578J June 2003 – September 2017 SN74AUP1G14
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 Switching Characteristics: CL = 5 pF
- 6.7 Switching Characteristics: CL = 10 pF
- 6.8 Switching Characteristics: CL = 15 pF
- 6.9 Switching Characteristics: CL = 30 pF
- 6.10 Operating Characteristics
- 6.11 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8 Detailed Description
8.1 Overview
This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching-noise immunity at the input.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
8.2 Functional Block Diagrams
Figure 4. Logic Diagram (Positive Logic)(DBV, DCK, DRL, DRY, DSF, DPW, and YZP Packages)
Figure 5. Logic Diagram (Positive Logic)(YFP Package)
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device creates fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings table must be followed at all times.
8.3.2 Schmitt-Trigger Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics table, using ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs slowly will also increase dynamic current consumption of the device. For additional information regarding Schmitt-trigger inputs, see Understanding Schmitt Triggers.
8.3.3 Clamp Diodes
The inputs and outputs to this device have negative clamping diodes.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
Figure 6. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.4 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high impedance state when the supply voltage is 0 V. The maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical Characteristics table.
8.3.5 Over-Voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum input voltage value specified in the Absolute Maximum Ratings table.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74AUP1G14.
Table 1. Function Table
| INPUT A |
OUTPUT Y |
|---|---|
| H | L |
| L | H |