SCES568I June 2004 – September 2016 SN74AUP1G02
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 Switching Characteristics, CL = 5 pF
- 6.7 Switching Characteristics, CL = 10 pF
- 6.8 Switching Characteristics, CL = 15 pF
- 6.9 Switching Characteristics, CL = 30 pF
- 6.10 Operating Characteristics
- 6.11 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機械數(shù)據(jù) (封裝 | 引腳)
- DPW|5
- DBV|5
- DSF|6
- DCK|5
- YFP|6
- DRL|5
- DRY|6
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
8 Detailed Description
8.1 Overview
The SN74LVC1G02 device contains one 2-input positive-NOR gate and performs the Boolean function Y = A + B or Y = A × B.
The AUP family of devices has quiescent power consumption less than 1 µA and comes in the ultra small DPW package. The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves significant board space over other package options while still retaining the traditional manufacturing friendly lead pitch of 0.5 mm.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered. The Ioff feature also allows for live insertion.
8.2 Functional Block Diagram
8.3 Feature Description
- Wide operating VCC range of 0.8 V to 3.6 V
- 3.6-V I/O tolerant to support down translation
- Input hysteresis allows slow input transition and better switching noise immunity at the input
- Ioff feature allows voltages on the inputs and outputs when VCC is 0 V
- Low noise due to slower edge rates
8.4 Device Functional Modes
Table 1 shows the functional modes of SN74AUP1G02.
Table 1. Function Table
| INPUTS | OUTPUT Y |
|
|---|---|---|
| A | B | |
| L | L | H |
| L | H | L |
| H | L | L |
| H | H | L |