ZHCSCM6G May 2014 – October 2019 SN65HVD70 , SN65HVD71 , SN65HVD73 , SN65HVD74 , SN65HVD76 , SN65HVD77
PRODUCTION DATA.
Internal ESD protection circuits protect the transceiver against Electrostatic Discharges (ESD) according to IEC61000-4-2 of up to ±12 kV, and against electrical fast transients (EFT) according to IEC61000-4-4 of up to ±4 kV.
The SN65HVD7x full-duplex family provides internal biasing of the receiver input thresholds in combination with large input-threshold hysteresis. At a positive input threshold of VIT+ = –20 mV and an input hysteresis of Vhys = 40 mV, the receiver output remains logic high under a bus-idle or bus-short condition even in the presence of 120 mVPP differential noise without the need for external failsafe biasing resistors.
Device operation is specified over a wide temperature range from –40°C to 125°C.