ZHCSE15F July 2015 – May 2018 SN65DP159 , SN75DP159
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| tr | Rise time of both SDA and SCL signals | Vcc = 3.3-V | 300 | ns | ||
| tf | Fall time of both SDA and SCL signals | 300 | ns | |||
| tHIGH | Pulse duration, SCL high | 0.6 | μs | |||
| tLOW | Pulse duration, SCL low | 1.3 | μs | |||
| tSU1 | Setup time, SDA to SCL | 100 | ns | |||
| tST, STA | Setup time, SCL to start condition | 0.6 | μs | |||
| tHD,STA | Hold time, start condition to SCL | 0.6 | μs | |||
| tST,STO | Setup time, SCL to stop condition | 0.6 | μs | |||
| t(BUF) | Bus free time between stop and start condition. | 1.3 | μs | |||
| tPLH1 | Propagation delay time, low-to-high-level output | Source-to-sink: 100-kbps pattern;
Cb(Sink) = 400-pF(1); See Figure 18 |
360 | ns | ||
| tPHL1 | Propagation delay time, high-to-low-level output | 230 | ns | |||
| tPLH2 | Propagation delay time, low-to-high-level output | Sink to Source: 100-kbps pattern;
Cb(Source) = 100-pF(1); See Figure 19 |
250 | ns | ||
| tPHL2 | Propagation delay time, high-to-low-level output | 200 | ns | |||