ZHCSEQ7C February 2016 – December 2021 SN65DP141
PRODUCTION DATA
| PARAMETER | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|
| fSCL | SCL clock frequency | 400 | KHz | |||
| tBUF | Bus free time between START and STOP conditions | 1.3 | μs | |||
| tHDSTA | "Hold time after repeated START
condition. After this period, the first clock pulse is generated |
0.6 | μs | |||
| tLOW | Low period of the SCL clock | 1.3 | μs | |||
| tHIGH | High period of the SCL clock | 0.6 | μs | |||
| tSUSTA | Setup time for a repeated START condition | 0.6 | μs | |||
| tHDDAT | Data HOLD time | 0 | μs | |||
| tSUDAT | Data setup time | 100 | μs | |||
| tR | Rise time of both SDA and SCL signals | 300 | μs | |||
| tF | Fall time of both SDA and SCL signals | 300 | μs | |||
| tSUSTO | Setup time for STOP condition | 0.6 | μs | |||