5.1 Functional Block Diagram

Figure 5-1 shows the functional block diagram.

Figure 5-1 Functional Block Diagram

5.2 Serial Communication Interface

A "dual-mode" serial communication interface supports either SPI or I²C communication. The serial interface allows writing and reading the internal NDEF memory as well as configuring the device operation.

5.3 SPI or I²C Mode Selection

The selection between I²C or SPI mode takes place during the power-up and initialization phase of the device based on the input level at pin SCMS/CS (see Table 5-1).

During initialization, an integrated pullup resistor pulls SCMS/CS high, which makes SPI the default interface. To enable I²C, this pin must be tied low externally. The pullup resistor is disabled after initialization to avoid any current through the resistor during normal operation. In SPI mode, the pin reverts to its CS functionality after initialization.

5.4 Communication Protocol

The tag is programmed and controlled by writing data into and reading data from the address map shown in Table 5-2 via the serial interface (SPI or I²C).

5.5 I²C Protocol

A command is always initiated by the master by addressing the device using the specified I²C device address. The device address is a 7-bit I²C address. The upper 4 bits are hard-coded, and the lower 3 bits are programmable by the input pins E0 through E2.

To write data, the device is addressed using the specified I²C device address with R/W = 0, followed by the upper 8 bits of the first address to be written and the lower 8 bits of that address. Next (without a repeated start), the data to be written starting at the specified address is received. With each data byte received, the address is automatically incremented by 1. The write access is terminated by the STOP condition on the I²C bus.

Figure 5-2 I²C Write Access

To read data, the device is addressed using the specified I²C device address with R/W = 0, followed by the upper 8 bits of the first address to be read and then the lower 8 bits of that address. Next, a repeated start condition is expected with the I²C device address and R/W = 1. The device then transmit data starting at the specified address until a non-acknowledgment and a STOP condition is received.

Figure 5-3 I²C Read Access

The following figures show examples of I²C accesses to the Control register at address 0xFFFE.

Figure 5-4 I²C Access Example: Write of the Control Register at Address 0xFFFE With 0x00, 0x02 (RF Enable = 1)

Figure 5-5 I²C Access Example: Read of the Control Register at Address 0xFFFE, Responds With 0x00, 0x02 (RF Enable = 1)

5.6 SPI Protocol

The SPI communication mode (SCK idle state and clock phase) is selected by tying E0 and E1 to VSS or VCC according to Table 5-6.

An SPI communication is always initiated by the master by pulling the CS pin low.

To write data into the device, this is followed by the master sending a write command (0x02) followed by the upper 8 bits of the first address to be written and then the lower 8 bits of that address. Next, the data to be written starting at the specified address is received. With each data byte received, the address is automatically incremented by 1. The write access is terminated by pulling the CS pin high.

Figure 5-6 SPI Write Access

To read data from the device, pulling the CS pin low is followed by the master sending a read command (0x03 or 0x0B) followed by the upper 8 bits of the first address to be read, the lower 8 bits of that address, and a dummy byte. The device responds with the data that is read starting at the specified address until the CS pin is pulled high.

Figure 5-7 SPI Read Access (Command: 0x03 or 0x0B)

Commands other than write (0x02) and read (0x03 or 0x0B) are ignored. There is no difference in using the read command 0x03 or 0x0B.

Figure 5-8 and Figure 5-9 show examples of SPI accesses to the Control register at address 0xFFFE.

Figure 5-8 SPI Access Example: Write of the Control Register at Address 0xFFFE With 0x00, 0x02 (RF Enable = 1)

Figure 5-9 SPI Access Example: Read of the Control Register at Address 0xFFFE, Responds With 0x00, 0x02 (RF Enable = 1)

5.7 Registers

5.8 NFC Type-4 Tag Functionality

This device is an ISO14443B-compliant transponder that operates according to the NFC Forum Tag Type-4 specification and supports the NFC Forum NDEF (NFC Data Exchange Format) requirements. Through the RF interface, the user can read and update the contents in the NDEF memory. The contents in the NDEF memory (stored in SRAM) are stored as long as power is maintained.

This device does not support the peer-to-peer or reader/writer modes in the ISO18092/NFC Forum specification. All RF communication between an NFC forum device and this device is in the passive tag mode. The device responds by load modulation and is not considered an intentional radiator.

This device is intended to be used in applications where the primary reader/writer is for example an NFC-enabled cell phone. The device enables data transfer to and from an NFC phone by RF to the host application that is enabled with the dual interface device. In this case, the host application can be considered the destination device, and the cell phone or other type of mobile device is treated as the end-point device.

This device supports ISO14443-3, ISO14443-4, and NFC Forum commands as described in the following sections. A high-level overview of the ISO14443B and NFC commands and responses are shown in Figure 5-10.

106-kbps, 212-kbps, 424-kbps, and 848-kbps data rates are supported.

The device always answers ATTRIB commands from the PCD that request higher data rates. Note, this is not NFC-compliant, because for NFC-B the maximum data rate specified is 106 kbps. It is assumed that an NFC-compliant PCD would not request higher data rates thus no interoperability issues are expected.

Even though all data rates up to 848 kbps are supported, the device by default reports only the capability to support 106 kbps to the PCD. To change this behavior, use the sequence described in Section 5.8.3.

The ISO14443B command and response structure is detailed in ISO14443-3, ISO14443-4, and NFC Forum-TS-Digital Protocol. The applicable ISO7816-4 commands are detailed in NFC Forum-TS-Type-4-Tag_2.0.

Figure 5-10 Command and Response Exchange Flow

5.9 NDEF Memory

This device implements 3KB of SRAM memory that must be written with the NDEF Application data.

Table 5-31 shows the mandatory structure. The data can be accessed through the RF interface only after the NDEF memory is correctly initialized through the serial interface (I²C or SPI).

While writing into the NDEF memory, the RF interface must be disabled by clearing the Enable RF bit in the General Control register. After the NDEF memory is properly initialized, the RF interface can be enabled be setting the Enable RF bit in the General Control register to 1. When the RF interface is enabled, the basic NDEF structure is checked for correctness. If an error in the structure is detected, the NDEF Error IRQ is triggered, and the RF interface remains disabled (the Enable RF bit in the General Control register is cleared to 0).

If the NDEF application data must be modified through the serial interface after the RF interface is enabled, it is recommended to read the RF Busy bit in the Status register. If the RF interface is busy, defer disabling the RF interface until the RF transaction is completed (indicated by RF Busy bit = 0).

Figure 5-11 shows the recommended flow how to control the access to the NDEF memory.

The address range for the NDEF memory is 0x0000 to 0x0BFF.

Figure 5-11 Recommended NDEF Memory Flow

5.10 Typical Usage Scenario

A typical usage scenario is as follows:

1. Write capability container and messages into the NDEF memory (starting from address 0) using the serial interface.
2. Enable interrupts (especially End of Read and End of Write).
3. Configure the interrupt pin INTO as needed and enable the RF interface.
4. Wait for interrupt signaled by INTO.
5. Disable RF interface (but keep INTO settings unchanged).
6. Read interrupt flag register to determine interrupt sources.
7. Clear interrupt flags. INTO returns to inactive state.
8. Read and modify NDEF memory as needed.
9. Enable RF interface again (keeping INTO settings unchanged) and continue with ⁽⁴⁾.

5.11 References

ISO/IEC 14443-2: 2001, Part 2: Radio frequency interface power and signal interface

ISO/IEC 14443-3: 2001, Part 3: Initialization and anticollision

ISO/IEC 14443-4: 2001, Part 4: Transmission protocols

ISO/IEC 18092, NFC Communication Interface and Protocol-1 (NFCIP-1)

ISO/IEC 21481, NFC Communication Interface Protocol-2 (NFCIP-2)

NDEF NFC Forum Spec, NFC Data Exchange Format Specification