ZHCSMY3 December 2020 PCM6020-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics
- 7.6 Timing Requirements:?I2C Interface
- 7.7 Switching Characteristics: I2C Interface
- 7.8 Timing Requirements:?SPI Interface
- 7.9 Switching Characteristics: SPI Interface
- 7.10 Timing Requirements:?TDM, I2S or LJ Interface
- 7.11 Switching Characteristics: TDM, I2S or LJ Interface
- 7.12 Timing Diagrams
- 7.13 Typical Characteristics
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Serial Interfaces
- 8.3.2 Phase-Locked Loop (PLL) and Clock Generation
- 8.3.3 Input Channel Configuration
- 8.3.4 Reference Voltage
- 8.3.5 Microphone Bias
- 8.3.6 Input DC Fault Diagnostics
- 8.3.7
Signal-Chain Processing
- 8.3.7.1 Programmable Channel Gain and Digital Volume Control
- 8.3.7.2 Programmable Channel Gain Calibration
- 8.3.7.3 Programmable Channel Phase Calibration
- 8.3.7.4 Programmable Digital High-Pass Filter
- 8.3.7.5 Programmable Digital Biquad Filters
- 8.3.7.6 Programmable Channel Summer and Digital Mixer
- 8.3.7.7
Configurable Digital Decimation Filters
- 8.3.7.7.1
Linear Phase Filters
- 8.3.7.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
- 8.3.7.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
- 8.3.7.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
- 8.3.7.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
- 8.3.7.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
- 8.3.7.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
- 8.3.7.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
- 8.3.7.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
- 8.3.7.7.1.9 Sampling Rate: 768 kHz or 705.6 kHz
- 8.3.7.7.2 Low-Latency Filters
- 8.3.7.7.3
Ultra-Low-Latency Filters
- 8.3.7.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
- 8.3.7.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
- 8.3.7.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
- 8.3.7.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
- 8.3.7.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
- 8.3.7.7.3.6 Sampling Rate: 192 kHz or 176.4 kHz
- 8.3.7.7.3.7 Sampling Rate: 384 kHz or 352.8 kHz
- 8.3.7.7.1
Linear Phase Filters
- 8.3.8 Automatic Gain Controller (AGC)
- 8.3.9 Interrupts, Status, and Digital I/O Pin Multiplexing
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6 Register Maps
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
8.5.1.1.2.1 I2C Single-Byte Write
As shown in Figure 8-67, a single-byte data write transfer begins with the master device transmitting a START condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write-data transfer, the read/write bit must be set to 0. After receiving the correct I2C slave address and the read/write bit, the device responds with an acknowledge bit (ACK). Next, the master device transmits the register byte corresponding to the device internal register address being accessed. After receiving the register byte, the device again responds with an acknowledge bit (ACK). Then, the master transmits the byte of data to be written to the specified register. When finished, the slave device responds with an acknowledge bit (ACK). Finally, the master device transmits a STOP condition to complete the single-byte data write transfer.
Figure 8-67 I2C Single-Byte Write Transfer