ZHCSMY3 December 2020 PCM6020-Q1
PRODUCTION DATA
This register page (shown in GUID-F389B178-7C9A-45BD-89E0-0B60D22BC172.html#T5453282-95) consists of the programmable coefficients for mixer 1 and mixer 2 and the first-order IIR filter. All mixer coefficients are 32-bit, two’s complement numbers using a 1.31 number format. The value of 0x7FFFFFFF is equivalent to +1 (0-dB gain), the value 0x00000000 is equivalent to mute (zero data) and all values in between set the mixer attenuation computed using GUID-F389B178-7C9A-45BD-89E0-0B60D22BC172.html#T5453191-22. If the MSB is set to '1' then the attenuation remains the same but the signal phase is inverted. All IIR filter programmable coefficients are 32-bit, two’s complement numbers. For a successful coefficient register transaction, the host device must write and read all four bytes starting with the most significant byte (BYT1) for a target coefficient register transaction. When using SPI for a coefficient register read transaction, the device transits the first byte as a dummy read byte; therefore, the host must read five bytes, including the first dummy read byte and the last four bytes corresponding to the coefficient register value starting with the most significant byte (BYT1).
| ADDRESS | ACRONYM | RESET VALUE | REGISTER DESCRIPTION |
|---|---|---|---|
| 0x00 | PAGE[7:0] | 0x00 | GUID-20201214-SS0T-JPVW-5ZTR-RTWVBJ4GW9B0.html#GUID-DDC1CAE0-C88B-4636-AB28-57820F74FE0E |
| 0x08 | MIX1_CH1_BYT1[7:0] | 0x7F | Digital mixer 1, channel 1 coefficient byte[31:24] |
| 0x09 | MIX1_CH1_BYT2[7:0] | 0xFF | Digital mixer 1, channel 1 coefficient byte[23:16] |
| 0x0A | MIX1_CH1_BYT3[7:0] | 0xFF | Digital mixer 1, channel 1 coefficient byte[15:8] |
| 0x0B | MIX1_CH1_BYT4[7:0] | 0xFF | Digital mixer 1, channel 1 coefficient byte[7:0] |
| 0x0C | MIX1_CH2_BYT1[7:0] | 0x00 | Digital mixer 1, channel 2 coefficient byte[31:24] |
| 0x0D | MIX1_CH2_BYT2[7:0] | 0x00 | Digital mixer 1, channel 2 coefficient byte[23:16] |
| 0x0E | MIX1_CH2_BYT3[7:0] | 0x00 | Digital mixer 1, channel 2 coefficient byte[15:8] |
| 0x0F | MIX1_CH2_BYT4[7:0] | 0x00 | Digital mixer 1, channel 2 coefficient byte[7:0] |
| 0x18 | MIX2_CH1_BYT1[7:0] | 0x00 | Digital mixer 2, channel 1 coefficient byte[31:24] |
| 0x19 | MIX2_CH1_BYT2[7:0] | 0x00 | Digital mixer 2, channel 1 coefficient byte[23:16] |
| 0x1A | MIX2_CH1_BYT3[7:0] | 0x00 | Digital mixer 2, channel 1 coefficient byte[15:8] |
| 0x1B | MIX2_CH1_BYT4[7:0] | 0x00 | Digital mixer 2, channel 1 coefficient byte[7:0] |
| 0x1C | MIX2_CH2_BYT1[7:0] | 0x7F | Digital mixer 2, channel 2 coefficient byte[31:24] |
| 0x1D | MIX2_CH2_BYT2[7:0] | 0xFF | Digital mixer 2, channel 2 coefficient byte[23:16] |
| 0x1E | MIX2_CH2_BYT3[7:0] | 0xFF | Digital mixer 2, channel 2 coefficient byte[15:8] |
| 0x1F | MIX2_CH2_BYT4[7:0] | 0xFF | Digital mixer 2, channel 2 coefficient byte[7:0] |
| 0x48 | IIR_N0_BYT1[7:0] | 0x7F | Programmable first-order IIR, N0 coefficient byte[31:24] |
| 0x49 | IIR_N0_BYT2[7:0] | 0xFF | Programmable first-order IIR, N0 coefficient byte[23:16] |
| 0x4A | IIR_N0_BYT3[7:0] | 0xFF | Programmable first-order IIR, N0 coefficient byte[15:8] |
| 0x4B | IIR_N0_BYT4[7:0] | 0xFF | Programmable first-order IIR, N0 coefficient byte[7:0] |
| 0x4C | IIR_N1_BYT1[7:0] | 0x00 | Programmable first-order IIR, N1 coefficient byte[31:24] |
| 0x4D | IIR_N1_BYT2[7:0] | 0x00 | Programmable first-order IIR, N1 coefficient byte[23:16] |
| 0x4E | IIR_N1_BYT3[7:0] | 0x00 | Programmable first-order IIR, N1 coefficient byte[15:8] |
| 0x4F | IIR_N1_BYT4[7:0] | 0x00 | Programmable first-order IIR, N1 coefficient byte[7:0] |
| 0x50 | IIR_D1_BYT1[7:0] | 0x00 | Programmable first-order IIR, D1 coefficient byte[31:24] |
| 0x51 | IIR_D1_BYT2[7:0] | 0x00 | Programmable first-order IIR, D1 coefficient byte[23:16] |
| 0x52 | IIR_D1_BYT3[7:0] | 0x00 | Programmable first-order IIR, D1 coefficient byte[15:8] |
| 0x53 | IIR_D1_BYT4[7:0] | 0x00 | Programmable first-order IIR, D1 coefficient byte[7:0] |