ZHCSMY3 December 2020 PCM6020-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics
- 7.6 Timing Requirements:?I2C Interface
- 7.7 Switching Characteristics: I2C Interface
- 7.8 Timing Requirements:?SPI Interface
- 7.9 Switching Characteristics: SPI Interface
- 7.10 Timing Requirements:?TDM, I2S or LJ Interface
- 7.11 Switching Characteristics: TDM, I2S or LJ Interface
- 7.12 Timing Diagrams
- 7.13 Typical Characteristics
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Serial Interfaces
- 8.3.2 Phase-Locked Loop (PLL) and Clock Generation
- 8.3.3 Input Channel Configuration
- 8.3.4 Reference Voltage
- 8.3.5 Microphone Bias
- 8.3.6 Input DC Fault Diagnostics
- 8.3.7
Signal-Chain Processing
- 8.3.7.1 Programmable Channel Gain and Digital Volume Control
- 8.3.7.2 Programmable Channel Gain Calibration
- 8.3.7.3 Programmable Channel Phase Calibration
- 8.3.7.4 Programmable Digital High-Pass Filter
- 8.3.7.5 Programmable Digital Biquad Filters
- 8.3.7.6 Programmable Channel Summer and Digital Mixer
- 8.3.7.7
Configurable Digital Decimation Filters
- 8.3.7.7.1
Linear Phase Filters
- 8.3.7.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
- 8.3.7.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
- 8.3.7.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
- 8.3.7.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
- 8.3.7.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
- 8.3.7.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
- 8.3.7.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
- 8.3.7.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
- 8.3.7.7.1.9 Sampling Rate: 768 kHz or 705.6 kHz
- 8.3.7.7.2 Low-Latency Filters
- 8.3.7.7.3
Ultra-Low-Latency Filters
- 8.3.7.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
- 8.3.7.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
- 8.3.7.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
- 8.3.7.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
- 8.3.7.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
- 8.3.7.7.3.6 Sampling Rate: 192 kHz or 176.4 kHz
- 8.3.7.7.3.7 Sampling Rate: 384 kHz or 352.8 kHz
- 8.3.7.7.1
Linear Phase Filters
- 8.3.8 Automatic Gain Controller (AGC)
- 8.3.9 Interrupts, Status, and Digital I/O Pin Multiplexing
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6 Register Maps
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
8.3.1.2.3 Left-Justified (LJ) Interface
The standard LJ protocol is defined for only two channels: left and right. The device extends the same protocol timing for multichannel operation. In LJ mode, the MSB of the left slot 0 is transmitted in the same BCLK cycle after the rising edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK. Immediately after the left slot 0 data transmission, the remaining left slot data are transmitted in order. The MSB of the right slot 0 is transmitted in the same BCLK cycle after the falling edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK. Immediately after the right slot 0 data transmission, the remaining right slot data are transmitted in order. FSYNC is transmitted on the falling edge of BCLK. Figure 8-9 to Figure 8-12 illustrate the protocol timing for LJ operation with various configurations.
Figure 8-9 LJ Mode Standard Protocol Timing (TX_OFFSET = 0)
Figure 8-10 LJ Protocol Timing (TX_OFFSET = 2)
Figure 8-11 LJ Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 0)
Figure 8-12 LJ Protocol Timing (TX_OFFSET = 1 and BCLK_POL = 1)For proper operation of the audio bus in LJ mode, the number of bit clocks per frame must be greater than or equal to the number of active output channels (including left and right slots) times the programmed word length of the output channel data. The device FSYNC high pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active left slots times the data word length configured. Similarly, the FSYNC low pulse must be a number of BCLK cycles wide that is greater than or equal to the number of active right slots times the data word length configured. For a higher BCLK frequency operation, using LJ mode with a TX_OFFSET value higher than 0 is recommended.