ZHCSPD5A April 2022 – September 2022 PCM5120-Q1
PRODUCTION DATA
The device integrates a dynamic range compressor (DRC) to amplify low-level signals and limits the maximum signal amplitude at the output. This algorithm is implemented with very low latency and all signal chain blocks are designed to minimize any audible artifacts that may occur resulting from dynamic gain modulation. The host can configure the target signal threshold level at which the DRC is triggered by setting the appropriate value for the DRE_LVL[3:0] (P0_R109[7:4]) register bits. Table 8-47 lists the DRE_LVL configuration settings.
| P0_R109_D[7:4] : DRE_LVL[3:0] | DRC TRIGGER THRESHOLD LEVEL |
|---|---|
| 0000 | The DRC trigger threshold is the –12-dB input signal level |
| 0001 | The DRC trigger threshold is the –18-dB input signal level |
| 0010 | The DRC trigger threshold is the –24-dB input signal level |
| … | … |
| 0111 (default) | The DRC trigger threshold is the –54-dB input signal level |
| … | … |
| 1001 | The DRC trigger threshold is the –66-dB input signal level |
| 1010 to 1111 | Reserved (do not use these settings) |
The DRC gain range can be dynamically modulated by using the DRE_MAXGAIN[3:0] (P0_R109[3:0]) register bits. Table 8-48 lists the DRE_MAXGAIN configuration settings.
| P0_R109_D[3:0] : DRE_MAXGAIN[3:0] | DRC MAXIMUM GAIN ALLOWED |
|---|---|
| 0000 | The DRC maximum gain allowed is 2 dB |
| 0001 | The DRC maximum gain allowed is 4 dB |
| 0010 | The DRC maximum gain allowed is 6 dB |
| … | … |
| 1011 (default) | The DRC maximum gain allowed is 24 dB |
| … | … |
| 1110 | The DRC maximum gain allowed is 30 dB |
| 1111 | Reserved (do not use this setting) |
The DRC scheme is only supported for analog microphone recording channels with an AC-coupled input for best performance. Only one of the AGC, DRC, or DRE features can be enabled at a time. The device can be configured in DRC mode by setting DRC_EN (P0_R108_D1) to 1'b1. The DRC scheme can be independently enabled or disabled for each channel using the CH1_DREEN (P0_R60_D0) and CH2_DREEN (P0_R65_D0) register bits. For a DC-coupled input, the DRC scheme can be used with limited DRE_MAXGAIN depending on the DC differential input common-mode offset.
Only change the DRC configuration registers before powering up the device. Enabling the DRC for processing increases the power consumption of the device because of increased signal processing. Therefore, disable the DRC for low-power critical applications. Furthermore, the DRC is not supported for output sample rates greater than 192 kHz.