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SBAS452A September 2008 – January 2016 PCM3168A

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

PAP|64
- MPQF071C

散熱焊盤機械數據 (封裝 | 引腳)

PAP|64
- PPTD128G

訂購信息

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted).⁽¹⁾

		MIN	MAX	UNIT
Supply voltage	VCCAD1	–0.3	6.5	V
	VCCAD2	–0.3	6.5
	VCCDA1	–0.3	6.5
	VCCDA2	–0.3	6.5
	VDD1	–0.3	4
	VDD2	–0.3	4
Ground voltage differences	AGNDAD1	–0.1	0.1	V
	AGNDAD2	–0.1	0.1
	AGNDDA1	–0.1	0.1
	AGNDDA2	–0.1	0.1
	DGND1	–0.1	0.1
	DGND2	–0.1	0.1
Supply voltage differences	VCCAD1	–0.1	0.1	V
	VCCAD2	–0.1	0.1
	VCCDA1	–0.1	0.1
	VCCDA2	–0.1	0.1
	VDD1	–0.1	0.1
	VDD2	–0.1	0.1
Digital input voltage	RST	–0.3	6.5	V
	MS	–0.3	6.5
	MC	–0.3	6.5
	MDI	–0.3	6.5
	SCK	–0.3	6.5
	BCKAD/DA	–0.3	(V_DD + 0.3) < +4.0
	LRCKAD/DA	–0.3	(V_DD + 0.3) < +4.0
	DIN1/2/3/4	–0.3	(V_DD + 0.3) < +4.0
	DOUT1/2/3	–0.3	(V_DD + 0.3) < +4.0
	MODE	–0.3	(V_DD + 0.3) < +4.0
	OVF	–0.3	(V_DD + 0.3) < +4.0
	ZERO	–0.3	(V_DD + 0.3) < +4.0
	MDO	–0.3	(V_DD + 0.3) < +4.0
Analog input voltage	VIN1-6±	–0.3	(V_CC + 0.3) < +6.5	V
	VCOMAD/DA	–0.3	(V_CC + 0.3) < +6.5
	VOUT1-8±	–0.3	(V_CC + 0.3) < +6.5
	VREFAD1/2	–0.3	(V_CC + 0.3) < +6.5
Input current (all pins except supplies)		–10	10	mA
Ambient temperature range (under bias)		–40	125	°C
Junction temperature			150	°C
Lead temperature (soldering, 5s)			260	°C
Package temperature (IR reflow, peak)			260	°C
Storage temperature, T_stg		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±4000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±750	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted).

			MIN	NOM	MAX	UNIT
V_CC	Analog supply voltage		4.5	5.0	5.5	V
V_DD	Digital supply voltage		3.0	3.3	3.6	V
Digital Interface			LVTTL compatible
Digital input clock frequency		Sampling frequency, LRCKAD/LRCKDA⁽¹⁾	8		96/192⁽¹⁾	kHz
Digital input clock frequency		System clock frequency, SCKI	2.048		36.864	MHz
V_I	Analog input level	Single-ended		1		V_RMS
V_I	Analog input level	Differential		2		V_RMS
V_O	Analog output voltage	Differential		8		V_PP
V_OLR	Analog output load resistance	To AC-coupled GND	5			kΩ
V_OLR	Analog output load resistance	To DC-coupled GND	15			kΩ
V_OLC	Analog output load capacitance				50	pF
D_OLC	Digital output load capacitance				20	pF
T_A	Operating free-air temperature	PCM3168A Consumer grade	–40	25	85	°C

(1) 192 kHz is supported only for DAC.

8.4 Thermal Information

THERMAL METRIC⁽¹⁾		PCM3168A	UNIT
		PAP (HTQFP)
		64 PINS
R_θJA	Junction-to-ambient thermal resistance	26.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	7.7	°C/W
R_θJB	Junction-to-board thermal resistance	8.9	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	8.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics

At T_A = 25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, f_S = 48 kHz, SCKI = 512 f_S, 24-bit data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DATA FORMAT
	Audio data interface format		I²S, LJ, RJ, DSP, TDM
	Audio data word length			16, 24		Bits
	Audio data format		MSB first, twos complement
f_S	Sampling frequency, ADC		8	48	96	kHz
f_S	Sampling frequency, DAC		8	48	192	kHz
	System clock frequency	128 f_S, 192 f_S, 256 f_S, 384 f_S, 512 f_S, 768 f_S	2.048		36.864	MHz
INPUT LOGIC
V_IH⁽¹⁾⁽²⁾	Input logic level		2		V_DD	VDC
V_IL⁽¹⁾⁽²⁾	Input logic level				0.8	VDC
V_IH⁽³⁾⁽⁴⁾	Input logic level		2		5.5	VDC
V_IL⁽³⁾⁽⁴⁾	Input logic level				0.8	VDC
I_IH⁽²⁾⁽³⁾	Input logic level	V_IN = V_DD			±10	μA
I_IL⁽²⁾⁽³⁾	Input logic level	V_IN = 0 V			±10	μA
I_IH⁽¹⁾⁽⁴⁾	Input logic level	V_IN = V_DD		65	100	μA
I_IL⁽¹⁾⁽⁴⁾	Input logic level	V_IN = 0 V			±10	μA
OUTPUT LOGIC
V_OH⁽⁵⁾	Output logic level	I_OUT = –4 mA	2.4			VDC
V_OL⁽⁵⁾⁽⁶⁾	Output logic level	I_OUT = 4 mA			0.4	VDC
REFERENCE INPUT/OUTPUT
	VREFAD1 output voltage			VCCAD1		V
	VREFAD2 output voltage			AGNDAD1		V
	VCOMAD output voltage			0.5 × VCCAD1		V
	VCOMAD output impedance			10		kΩ
	Allowable VCOMAD output source/sink current				1	μA
	VCOMDA output voltage			0.5 × VCCDA1		V
	VCOMDA output impedance			7.5		kΩ
	Allowable VCOMDA output source/sink current				1	μA
ADC CHARACTERISTICS
	Resolution		16	24		Bits
	Full-scale input voltage	V_IN = 0 dB, Single-ended		0.2 × VCCAD1		V_RMS
	Full-scale input voltage	V_IN = 0 dB, Differential		0.4 × VCCAD1		V_RMS
	Center voltage			0.5 × VCCAD1		V
	Input impedance			45		kΩ
	Common-mode rejection ratio			80		dB
DC ACCURACY
	Gain mismatch channel-to-channel	Full-scale input, V_IN		±2.0	±6	% of FSR
	Gain error	Full-scale input, V_IN		±2.0	±6	% of FSR
	Bipolar zero error	Highpass filter bypass, V_IN		±1.0		% of FSR
DYNAMIC PERFORMANCE⁽⁷⁾⁽⁸⁾
	THD+N, V_IN = –1 dB	f_S = 48 kHz, Differential		–93	–87	dB
		f_S = 96 kHz, Differential		–93
		f_S = 48 kHz, Single-ended		–93
		f_S = 96 kHz, Single-ended		–93
	Dynamic range	f_S = 48 kHz, A-weighted, differential	100	107		dB
		f_S = 96 kHz, A-weighted, differential		107
		f_S = 48 kHz, A-weighted, single-ended		104
		f_S = 96 kHz, A-weighted, single-ended		104
	S/N ratio	f_S = 48 kHz, A-weighted, differential	100	107		dB
		f_S = 96 kHz, A-weighted, differential		107
		f_S = 48 kHz, A-weighted, single-ended		104
		f_S = 96 kHz, A-weighted, single-ended		104
	Channel separation (between one channel and others)	f_S = 48 kHz, Differential	98	104		dB
		f_S = 96 kHz, Differential		104
		f_S = 48 kHz, Single-ended		101
		f_S = 96 kHz, Single-ended		101
DIGITAL FILTER PERFORMANCE
	Passband (single)				0.454 × f_S	Hz
	Passband (dual)				0.454 × f_S	Hz
	Stop band (single)		0.555 × f_S			Hz
	Stop band (dual)		0.597 × f_S			Hz
	Passband ripple	< 0.454 × f_S, 0.454 × f_S			±0.035	dB
	Stop band attenuation	> 0.555 × f_S, 0.597 × f_S	–75			dB
	Group delay time (single)			27 / f_S		sec
	Group delay time (dual)			17 / f_S		sec
	Highpass filter frequency response	–3 dB		0.02 × f_S / 1000		Hz
DAC CHARACTERISTICS
	Resolution		16	24		Bits
DC ACCURACY
	Gain mismatch channel-to-channel			±2.0	±6	% of FSR
	Gain error			±2.0	±6	% of FSR
	Bipolar zero error			±1.0		% of FSR
DYNAMIC PERFORMANCE⁽⁹⁾⁽¹⁰⁾
	THD+N, V_OUT = 0 dB	f_S = 48 kHz		–94	–88	dB
		f_S = 96 kHz		–94
		f_S = 192 kHz		–94
	Dynamic range	f_S = 48 kHz, EIAJ, A-weighted	105	112		dB
		f_S = 96 kHz, EIAJ, A-weighted		112
		f_S = 192 kHz, EIAJ, A-weighted		112
	S/N ratio	f_S = 48 kHz, EIAJ, A-weighted	105	112		dB
		f_S = 96 kHz, EIAJ, A-weighted		112
		f_S = 192 kHz, EIAJ, A-weighted		112
	Channel separation (between one channel and others)	f_S = 48 kHz	102	108		dB
		f_S = 96 kHz		108
		f_S = 192 kHz		108
ANALOG OUTPUT
	Output voltage	Differential		1.6 × VCCDA1		V_PP
	Center voltage			0.5 × VCCDA1		V
	Load impedance	To AC-coupled GND⁽¹¹⁾	5			kΩ
	Load impedance	To DC-coupled GND⁽¹¹⁾	15			kΩ
	Lowpass filter frequency response	f = 20 kHz		–0.04		dB
	Lowpass filter frequency response	f = 44 kHz		–0.18		dB
DIGITAL FILTER PERFORMANCE⁽¹²⁾		Slow roll-off
	Passband (single, dual)				0.454 × f_S	Hz
	Passband (quad)				0.432 × f_S	Hz
	Stop band (single, dual)		0.546 × f_S			Hz
	Stop band (quad)		0.569 × f_S			Hz
	Passband ripple	≤ 0.454 × f_S			±0.0018	dB
	Stop band attenuation	> 0.546 × f_S, 0.569 × f_S	–75			dB
DIGITAL FILTER PERFORMANCE		Slow roll-off
	Passband				0.328 × f_S	Hz
	Stop band		0.673 × f_S			Hz
	Passband ripple	< 0.328 × f_S			±0.0013	dB
	Stop band attenuation	> 0.673 × f_S	–75			dB
DIGITAL FILTER PERFORMANCE⁽¹²⁾
	Group delay time (single, dual)			28/f_S		sec
	Group delay time (quad)			19/f_S		sec
	De-emphasis error			±0.1		dB
POWER-SUPPLY REQUIREMENTS
VCCxx1/2	Voltage range		4.5	5.0	5.5	VDC
VDD1/2	Voltage range		3.0	3.3	3.6	VDC
I_CC	Supply current	f_S = 48 kHz/ADC, f_S = 48 kHz/DAC		162	210	mA
		f_S = 96 kHz/ADC, f_S = 192 kHz/DAC		162		mA
		Full power-down⁽¹³⁾		300		μA
I_DD		f_S = 48 kHz/ADC, f_S = 48 kHz/DAC		106	130	mA
		f_S = 96 kHz/ADC, f_S = 192 kHz/DAC		127		mA
		Full power-down⁽¹³⁾		50		μA
	Power dissipation	f_S = 48 kHz/ADC, f_S = 48 kHz/DAC		1160	1480	mW
		f_S = 96 kHz/ADC, f_S = 192 kHz/DAC		1230
		f_S = 48 kHz/ADC, Power-down/DAC		660
		Power-down/ADC, f_S = 48 kHz/DAC		633
		Full power-down⁽¹³⁾		1.67
TEMPERATURE RANGE
	Operating temperature	PCM3168A Consumer grade	–40		85	°C
θ_JA	Thermal resistance	HTQFP-64		21		°C/W

(1) BCKAD, BCKDA, LRCKAD, and LRCKDA (in slave mode, Schmitt trigger input with 50-kΩ typical internal pulldown resistor).

(2) DIN1/2/3/4 and MDO/ADR1/MD1. (Except SPI mode, Schmitt trigger input).

(3) SCKI, MDI/SDA/DEMP, and MC/SCL/FMT (Schmitt trigger input, 5-V tolerant).

(4) RST and MS/ADR0/MD0 (Schmitt trigger input with 50-kΩ typical internal pulldown resistor, 5-V tolerant).

(5) BCKAD, BCKDA, LRCKAD, and LRCKDA (in master mode), DOUT1/2/3, ZERO, OVF, and MDO/ADR1/MD1 (in SPI mode).

(6) SDA (in I²C mode, open-drain low output).

(7) In differential mode at VINx± pin, f_IN = 1 kHz, using Audio Precision System II, RMS mode with 20-kHz lowpass filter and 400-Hz highpass filter.

(8) f_S = 48 kHz : SCKI = 512 f_S (single), f_S = 96 kHz : SCKI = 256 f_S (dual), f_S = 192 kHz : SCKI = 128 f_S (quad).

(9) In differential mode at VOUTx± pin, f_OUT = 1 kHz, using Audio Precision System II, RMS mode with 20-kHz lowpass filter and 400-Hz highpass filter.

(10) f_S = 48 kHz : SCKI = 512 f_S (single), f_S = 96 kHz : SCKI = 256 f_S (dual), f_S = 192 kHz : SCKI = 128 f_S (quad).

(11) Allowable minimum input resistance of differential to single-ended converter with D to S Gain = G is calculated as (1 + 2G)/(1 + G) × 5k for AC-coupled and (1+ 0.9G)/(1 + G) × 15k for DC-coupled connection, refer to Figure 61 and Figure 62 of the Application Information section.

(12) Exclude single and dual at 128 f_S, 192 f_S system clock and quad at 256 f_S to 768 f_S system clock, and specifications for quad, single, and dual are respectively applied in reverse for them.

(13) Halt SCKI, BCKAD, BCKDA, LRCKAD, and LRCKDA.

8.6 Timing Requirements: System Clock

Refer to Figure 1.

		MIN	MAX	UNIT
t_SCY	System clock pulse cycle time	27		ns
t_SCH	System clock pulse width high	10		ns
t_SCL	System clock pulse width low	10		ns
t_DTY	System clock pulse duty cycle	40%	60%

8.7 Timing Requirements: Power-On Reset

Refer to Figure 2.

		SINGLE	DUAL	QUAD	UNIT
t_DACDLY1	DAC delay time internal reset release to VOUT start	3600	7200	14400	Period of LRCKDA
t_DACDLY2	DAC fade-in/fade-out time	2048	4096	8192	Period of LRCKDA
t_ADCDLY1	ADC delay time internal reset release to DOUT start	4800	9600	N/A	Period of LRCKAD
t_ADCDLY2	ADC fade-in/fade-out time	2048	4096	N/A	Period of LRCKAD

8.8 Timing Requirements: Audio Interface for Left-Justified, Right-Justified, and I²S (Slave Mode)⁽¹⁾

Refer to Figure 3.

		MIN	MAX	UNIT
t_BCY	BCKAD/DA cycle time	75		ns
t_BCH	BCKAD/DA pulse width high	35		ns
t_BCL	BCKAD/DA pulse width low	35		ns
t_LRS	LRCKAD/DA setup time to BCKAD/DA rising edge	10		ns
t_LRH	LRCKAD/DA hold time to BCKAD/DA rising edge	10		ns
t_DIS	DIN1/2/3/4 setup time to BCKDA rising edge	10		ns
t_DIH	DIN1/2/3/4 hold time to BCKDA rising edge	10		ns
t_DOD	DOUT1/2/3 delay time from BCKAD falling edge	0	30	ns

(1) Load capacitance of output is 20 pF.

8.9 Timing Requirements: Audio Interface for Left-Justified, Right-Justified, and I²S (Master Mode)⁽¹⁾

Refer to Figure 4.

		MIN	TYP	MAX	UNIT
t_BCY	BCKAD/DA cycle time		1 / (64 × f_S)
t_BCH	BCKAD/DA pulse width high	0.4 × t_BCY	0.5 × t_BCY	0.6 × t_BCY
t_BCL	BCKAD/DA pulse width low	0.4 × t_BCY	0.5 × t_BCY	0.6 × t_BCY
t_LRD	LRCKAD/DA delay time from BCKAD/DA falling edge	–10		20	ns
t_DIS	DIN1/2/3/4 setup time to BCKDA rising edge	10			ns
t_DIH	DIN1/2/3/4 hold time to BCKDA rising edge	10			ns
t_DOD	DOUT1/2/3 delay time from BCKAD falling edge	–10		20	ns

(1) Load capacitance of output is 20 pF.

8.10 Timing Requirements: Audio Interface for DSP and TDM (Slave Mode)⁽¹⁾

Refer to Figure 5.

		MIN	MAX	UNIT
t_BCY	BCKAD cycle time	75		ns
t_BCY	BCKDA cycle time	40		ns
t_BCH	BCKAD pulse width high	35		ns
t_BCH	BCKDA pulse width high	15		ns
t_BCL	BCKAD pulse width low	35		ns
t_BCL	BCKDA pulse width low	15		ns
t_LRW	LRCKAD/DA pulse width high (DSP format)	t_BCY
t_LRW	LRCKAD/DA pulse width high (TDM format)	t_BCY	1 / f_S – t_BCY
t_LRS	LRCKAD/DA setup time to BCKAD/DA rising edge	10		ns
t_LRH	LRCKAD/DA hold time to BCKAD/DA rising edge	10		ns
t_DIS	DIN1/2/3/4 setup time to BCKDA rising edge	10		ns
t_DIH	DIN1/2/3/4 hold time to BCKDA rising edge	10		ns
t_DOD	DOUT1/2/3 delay time from BCKAD falling edge	0	30	ns

(1) Load capacitance of output is 20 pF.

8.11 Timing Requirements: Audio Interface for DSP and TDM (Master Mode)⁽¹⁾

Refer to Figure 6.

		MIN	TYP	MAX	UNIT
t_BCY	BCKAD/DA cycle time (DSP format)		1 / (64 × f_S)
	BCKAD/DA cycle time (TDM format, single rate)		1 / (256 × f_S)
	BCKAD/DA cycle time (TDM format, dual rate)		1 / (128 × f_S)
t_BCH	BCKAD/DA pulse width high	0.4 × t_BCY	0.5 × t_BCY	0.6 × t_BCY
t_BCL	BCKAD/DA pulse width low	0.4 × t_BCY	0.5 × t_BCY	0.6 × t_BCY
t_LRW	LRCKAD/DA pulse width high (DSP format)		t_BCY
t_LRW	LRCKAD/DA pulse width high (TDM format)		1 / (2 × f_S)
t_LRD	LRCKAD/DA delay time from BCKAD/DA falling edge	–10		20	ns
t_DIS	DIN1/2/3/4 setup time to BCKDA rising edge	10			ns
t_DIH	DIN1/2/3/4 hold time to BCKDA rising edge	10			ns
t_DOD	DOUT1/2/3 delay time from BCKAD falling edge	–10		20	ns

(1) Load capacitance of output is 20 pF.

8.12 Timing Requirements: DAC Outputs and ADC Outputs

Refer to Figure 7.

		SINGLE	DUAL	QUAD	UNIT
t_DACDLY3	DAC delay synchronization detect to normal data	38	38	29	Period of LRCKDA
t_ADCDLY3	ADC delay synchronization detect to normal data	60	60	N/A	Period of LRCKAD

8.13 Timing Requirements: Four-Wire Serial Control Interface⁽¹⁾

Refer to Figure 8.

		MIN	MAX	UNIT
t_MCY	MC pulse cycle time	100		ns
t_MCL	MC low-level time	40		ns
t_MCH	MC high-level time	40		ns
t_MHH	MS high-level time	t_MCY		ns
t_MSS	MS falling edge to MC rising edge	30		ns
t_MSH	MS rising edge from MC rising edge for LSB	15		ns
t_MDH	MDI hold time	15		ns
t_MDS	MDI setup time	15		ns
t_MDD	MDO enable or delay time from MC falling edge	0	30	ns
t_MDR	MDO disable time from MS rising edge	0	30	ns

(1) These timing parameters are critical for proper control port operation.

8.14 Timing Requirements: SCL and SDA Control Interface

Refer to Figure 9.

		STANDARD MODE		FAST MODE		UNIT
		MIN	MAX	MIN	MAX	UNIT
f_SCL	SCL clock frequency		100		400	kHz
t_BUF	Bus free time between STOP and START condition	4.7		1.3		μs
t_LOW	Low period of the SCL clock	4.7		1.3		μs
t_HI	High period of the SCL clock	4.0		0.6		μs
t_S-SU	Setup time for START/Repeated START condition	4.7		0.6		μs
t_S-HD	Hold time for START/Repeated START condition	4.0		0.6		μs
t_D-SU	Data setup time	250		100		ns
t_D-HD	Data hold time	0	3450	0	900	ns
t_SCL-R	Rise time of SCL signal		1000	20 + (0.1 × C_B)	300	ns
t_SCL-F	Fall time of SCL signal		1000	20 + (0.1 × C_B)	300	ns
t_SDA-R	Rise time of SDA signal		1000	20 + (0.1 × C_B)	300	ns
t_SDA-F	Fall time of SDA signal		1000	20 + (0.1 × C_B)	300	ns
t_P-SU	Setup time for STOP condition	4.0		0.6		μs
t_GW	Allowable glitch width		N/A		50
C_B	Capacitive load for SDA and SCL line		400		100	pF
V_NH	Noise margin at high level for each connected device (including hysteresis)	0.2 × V_DD		0.2 × V_DD		V
V_NL	Noise margin at low level for each connected device (including hysteresis)	0.1 × V_DD		0.1 × V_DD		V
V_HYS	Hysteresis of Schmitt-trigger input	N/A		0.05 × V_DD		V