9.3.1 Analog Inputs

The PCM3168A device includes six ADCs, each with individual pairs of differential voltage input pins, as shown in Table 1. Additionally, the PCM3168A device has the capability of single-ended inputs. The full-scale input voltage is (0.2 × VCCAD1) V_RMS at the single-ended input mode and (0.4 × VCCAD1) V_RMS at the differential input mode. The input mode is selected by the MODE pin in hardware control mode or by register settings in the software control mode. In single-ended mode, VINx+ pins are used and VINx– pins must be terminated with AGNDAD1/2 through a capacitor or terminated with VCOMAD.

9.3.2 Analog Outputs

The The PCM3168A device includes eight DACs, each with individual pairs of differential voltage inputs pins, as shown in Table 2. The full-scale output voltage is (1.6 × VCCDA1) V_PP in differential mode. DC-coupled loads are allowed in addition to ac-coupled loads if the load resistance conforms to the specification.

9.3.3 Voltage References

The PCM3168A device includes two internal references for the six-channel ADCs; these references correspond to the outputs VREFAD1 and VREFAD2. Both reference pins should be connected with an analog ground via decoupling capacitors. In addition, the PCM3168A device includes two pins for common-mode voltage output (VCOMDA for DACs and VCOMAD for ADCs). These pins should be also connected with an analog ground via decoupling capacitors. Furthermore, both common pins can be used to bias external high-impedance circuits, if they are required.

9.3.4 System Clock Input

The PCM3168A device requires an external system clock input applied at the SCKI input for ADC and DAC operation. The system clock operates at an integer multiple of the sampling frequency, or f_S. The multiples supported in ADC operation include 256 f_S, 384 f_S, 512 f_S, and 768 f_S; the multiples supported in DAC operation include 128 f_S, 192 f_S, 256 f_S, 384 f_S, 512 f_S, and 768 f_S. Details for these system clock multiples are shown in Table 3. Figure 1 shows the SCKI timing requirements.

9.3.5 Sampling Mode

The PCM3168A device supports two sampling modes (single rate and dual rate) in ADC operation, and three sampling modes (single rate, dual rate, and quad rate) in DAC operation. In single rate mode, the ADC and DAC operate at an oversampling frequency of x128 (except when SCKI = 128 f_S and 192 f_S). This mode is supported for sampling frequencies less than 50 kHz. In dual rate mode, the ADC and DAC operate at an oversampling frequency of x64; this mode is supported for sampling frequencies less than 100 kHz. In quad rate mode, the DAC operates at an oversampling frequency of x32. The sampling mode is automatically selected according to the ratio of system clock frequency and sampling frequency by default (for example, single rate for 512 f_S and 768 f_S, dual rate for 256 f_S and 384 f_S, and quad rate for 128 f_S and 192 f_S), but manual selection is also possible for specified combinations through the serial mode control resistor.

Table 4 and Figure 37 show the relation between the oversampling rate (OSR) of the ΔΣ modulator, noise-free shaped bandwidth, and each sampling mode setting for ADC operation. Table 5 and Figure 38 describe the relation between the oversampling rate of the digital filter and ΔΣ modulator, noise-free shaped bandwidth, and each sampling mode setting for DAC operation.

spacer

Figure 37. ADC ΔΣ Modulator and Digital Filter Characteristic

Figure 38. DAC ΔΣ Modulator and Digital Filter Characteristic

9.3.6 Reset Operation

The PCM3168A device has both an internal power-on reset circuit and an external reset circuit. The sequences for both reset circuits are illustrated in Figure 2, Timing Requirements: Power-On Reset, and Figure 39. Figure 2 and Timing Requirements: Power-On Reset describe the timing chart at the internal power-on reset. Initialization is triggered automatically at the point where V_DD exceeds 2.2 V typical, and the internal reset is released after 3846 SCKI clock cycles from power-on if RST is kept high and SCKI is provided. VOUT from the DACs are forced to the VCOMDA level initially (0.5 × VCCDA1) and settles at a specified level according to the rising V_CC. If synchronization among SCKI, BCKAD/DA, and LRCKAD/DA is maintained, VOUT starts to output with a fade-in sequence after t_DACDLY1 from the internal reset release; VOUT then provides an output that corresponds to DIN after (3846 SCKI + t_DACDLY1 + t_DACDLY2) from power-on. Meanwhile, DOUT from the ADCs begins to output with a fade-in sequence after t_ADCDLY1 from the internal reset release; DOUT then provides output corresponding to VIN after (3846 SCKI + t_ADCDLY1 + t_ADCDLY2) from power-on. If the synchronization is not held, the internal reset is not released and both operating modes are maintained at reset and power-down states; after the synchronization forms again, both the DAC and ADC return to normal operation with the above sequences.

Figure 39 illustrates a timing chart at the external reset. RST accepts an external forced reset by RST = low, and provides a device reset and power-down state that makes the lowest power dissipation state available in the PCM3168A device. If RST goes from high to low under synchronization among SCKI, BCKAD/DA, and LRCKAD/DA, the internal reset is asserted, all registers and memory are reset, and finally the PCM3168A device enters into an all power-down state. At the same time, VOUT is immediately forced into the AGNDDA1 level and DOUT becomes 0. To begin normal operation again, toggle RST high; the same power-up sequence as power-on reset shown in Figure 2 is performed.

The PCM3168A device does not require particular power-on sequences for V_CC and V_DD; it allows V_DD on and then V_CC on, or V_CC on and then V_DD on. From the viewpoint of the Absolute Maximum Ratings, however, simultaneous power-on is recommended for avoiding unexpected responses on VOUTx and DOUTx. Figure 2 illustrates the response for V_CC on with V_DD on.

Figure 39. External Reset Timing Requirements

9.3.7 Highpass Filter (HPF)

The PCM3168A device includes a highpass filter (HPF) for all ADC channels in order to remove the DC component of the digitized input signal. The filter is located at the output of the digital decimation filter. The –3-dB corner frequency for the HPF scales with the output sampling rate, where f_{–3 dB} = 0.020 × f_S/1000. When
f_S = 48 kHz, f_{–3 dB} is 0.96 Hz. The HPF function can be disabled (bypassed) by the BYP bits in two channels.

9.3.8 Overflow Flag

The PCM3168A device includes an overflow flag output for all ADC channels. As soon as any of the six-channel ADC digital outputs exceed the full-scale range, an overflow flag is forced high on the OVF pin. The overflow flag is held high for 1024 LRCKAD clock cycles. In parallel, overflow flag information is stored in the OVF bits of the mode control register, and the OVF bit is held until the mode control register is read. The overflow flag polarity can be changed by the OVFP bit. The OVF pin also indicates internal reset completion by transmitting a 4096 SCKI width pulse.

9.3.9 Zero Flag

The PCM3168A device includes a zero flag output for all DAC channels. When all of the eight-channel DACs digital inputs have continued as zero data for 1024 LRCKDA clock cycles, the zero flag is forced high on ZERO. In parallel, zero flag information is stored in the ZERO bits according to channel. The zero flag polarity can be changed by the ZREV bit. Also, the zero flag function can be selected by the AZRO bits. AND or OR logic for stereo, six channels, and eight channels can be selected.

9.3.10 Four-Wire (SPI) Serial Control

The PCM3168A device includes an SPI-compatible serial port that operates asynchronously with the audio serial interface. The control interface consists of MDI/SDA/DEMP, MDO/ADR1/MD1, MC/SCL/FMT, and MS/ADR0/MD0. MDI is the serial data input to program the mode control registers. MDO is the serial data output to read back register settings and some flags. MDO is inactive (Hi-Z, high impedance) during MS = high. MC is the serial bit clock that shifts the data into the control port. MS is the select input to enable the mode control port.

9.3.11 Control Data Word Format

All single write/read operations through the serial control port use 16-bit data words. Figure 40 shows the control data word format. The first bit is for read/write controls; 0 indicates a write operation and 1 indicates a read operation. Following the first bit are seven other bits, labeled ADR[6:0] that set the register address for the write/read operation. The eight least significant bits (LSBs), D[7:0] on MDI or MDO, contain the data to be written to the register specified by ADR[6:0], or the data read from the register specified by ADR[6:0].

Figure 40. Control Data Word Format for MDI

9.3.12 Register Write Operation

Figure 41 shows the functional timing diagram for single write operations on the serial control port. MS is held at a high state until a register must be written. To start the register write cycle, MS is set to a low state. 16 clocks are then provided on MC, corresponding to the 16 bits of the control data word on MDI. After the 16th clock cycle has been completed, MS is set high to latch the data into the indexed mode control register.

Also, the PCM3168A device supports multiple write operations in addition to single write operations, which can be performed by sending the following N-times of the 8-bit register data after the first 16-bit register address and register data while keeping the MC clocks and MS at a low state. Closing a multiple write operation can be accomplished by setting MS to a high state.

1.

NOINDENT:

X = Don't care

Figure 41. Register Write Operation

9.3.13 Register Read Operation

Figure 42 shows the functional timing diagram for single read operations on the serial control port. MS is held at a high state until a register must be read. To start the register read cycle, MS is set to a low state. 16 clocks are then provided on MC, corresponding to the first eight bits of the control data word on MDI and the second eight bits of the read-back data word from MDO. After the 16th clock cycle has been completed, MS is held high for the next write or read operation. MDO remains in a high impedance state except during the eight MC clock periods of the actual data transfer.

1.

NOINDENT:

X = Don't care

Figure 42. Register Read Operation

9.3.14 Two-Wire (I²C) Serial Control

The PCM3168A device supports an I²C-compatible serial bus and data transmission protocol for fast mode configured as a slave device. This protocol is explained in the I²C specification, version 2.0.

The PCM3168A device has a 7-bit slave address, as shown in Figure 43. The first five bits are the most significant bits (MSB) of the slave address and are factory-preset to 10001. The next two bits of the address byte are selectable bits that can be set by MS/ADR0/MD0 and MDO/ADR1/MD1. A maximum of four PCM3168A device can be connected on the same bus at any one time. Each device responds when it receives its own slave address.

Figure 43. Slave Address

9.3.15 Packet Protocol

A master device must control the packet protocol, which consists of the start condition, slave address with the read/write bit, data if a write operation is required, acknowledgement if a read operation is required, and stop condition. The PCM3168A device supports both slave receiver and transmitter functions. Details about DATA for both write and read operations are described in Figure 44.

1.

NOINDENT:

R/W: Read operation if 1; write operation otherwise.

2.

NOINDENT:

ACK: Acknowledgement of a byte if 0, not Acknowledgement of a byite if 1.

3.

NOINDENT:

DATA: Eight bits (byte); details are described in the Write Operation and Read Operation sections.

Figure 44. DATA Operation

9.3.16 Write Operation

The PCM3168A device supports a receiver function. A master device can write to any PCM3168A device register using single or multiple accesses. The master sends a PCM3168A device slave address with a write bit, a register address, and the data. If multiple access is required, the address is that of the starting register, followed by the data to be transferred. When the data are received properly, the index register is incremented by one automatically. When the index register reaches 0x5E, the next value is 0x40. When undefined registers are accessed, the PCM3168A device does not send an acknowledgment. Figure 45 illustrates a diagram of the write operation. The register address and write data are in 8-bit, MSB-first format.

1.

NOINDENT:

M = Master device, S = Slave device, St = Start condition, W = Write, ACK = Acknowledge, and Sp = Stop condition.

Figure 45. Framework for Write Operation

9.3.17 Read Operation

A master device can read the registers from 0x40 to 0x5E of the PCM3168A device. The value of the register address is stored in an indirect index register in advance. The master sends the PCM3168A slave address with a read bit after storing the register address. Then the PCM3168A device transfers the data of the register with address that is in the indirect index register. Figure 46 shows a diagram of the read operation.

1.

NOINDENT:

M = Master device, S = Slave device, St = Start condition, Sr = Repeated start condition, W = Write, R = Read, ACK = Acknowledge, NACK = Not acknowledge, and Sp = Stop condition.

NOINDENT:

NOTE: The slave address after the repeated start condition must be the same as the previous address.

Figure 46. Framework for Read Operation

9.4.1 Mode Control

The PCM3168A device includes four-way mode control selectable by MODE pin, as shown in Table 6. The pull-up and pull-down resistors must be 220 kΩ ±5%. This mode control selection is sampled only when the internal reset is released by a power-on reset or by a low-to-high transition of the external reset (RST pin); a system clock is also required.

From the mode control selection described in Table 6, the functions of four pins are changed, as shown in Table 7.

Both serial controls are available while RST = high and after internal reset completion, which is indicated as a negative transition (high ≥ low) of a 4096 × SCKI width pulse on the OVF pin.

9.4.2 Hardware Control Mode Configuration

The data format is selected by the MC/SCL/FMT pin between I²S format and I²S mode in TDM format, as shown in Table 8.

The de-emphasis filter is enabled by the MDI/SDA/DEMP pin. The de-emphasis frequency is fixed at 44.1 kHz in hardware control mode, as shown in Table 9. The software mode provides full selections of 32 kHz, 44.1 kHz, and 48 kHz.

The audio interface and the sampling mode are selected by the MS/ADR0/MD0 and MDO/ADR1/MD1 pins. The selectable multiple of the master mode audio interface is limited between 256 f_S, 384 f_S, and 512 f_S; the selectable sampling mode is limited as shown in Table 10. The software mode provides full selections.

9.4.3 Audio Serial Port Operation

The PCM3168A device audio serial port consists of 11 signals: BCKDA, BCKAD, LRCKDA, LRCKAD, DIN1, DIN2, DIN3, DIN4, DOUT1, DOUT2, and DOUT3. The PCM3168A device also supports audio-interface mode, slave mode, and master mode. The BCKAD/DA is a bit clock input at the slave mode and an output at the master mode. The LRCKAD/DA is a left/right word clock or frame synchronization clock input at slave mode and output at master mode. The DIN1/2/3/4 are the audio data inputs for the DAC. The DOUT1/2/3 are the audio data outputs from the ADC. BCKAD, LRCKAD and DOUT1/2/3 are used for the ADC, and BCKDA, LRCKDA and DIN1/2/3/4 are used for the DAC.

9.4.4 Audio Data Interface Formats and Timing

The PCM3168A device supports eight audio data interface formats for the ADC and DAC separately in both master and slave modes: 24-bit I²S, 24-bit left-justified, 24-bit right-justified, 16-bit right-justified, 24-bit left-justified mode DSP, 24-bit I²S mode DSP, 24-bit left-justified mode TDM, and 24-bit I²S mode TDM format. The PCM3168A device also supports two audio data interface formats for the DAC and slave mode: 24-bit left-justified mode high-speed TDM and 24-bit I²S mode high-speed TDM format. In the case of I²S, left-justified, and right-justified data formats, 64 BCKs, 48 BCKs, and 32 BCKs per LRCK period are supported, but 48 BCKs are limited in slave mode and 32 BCKs are limited in slave mode 16-bit right-justified only. In the case of TDM data format in single rate, BCKAD/DA, LRCKAD/DA, DOUT1, and DIN1 are used. In the case of TDM data format in dual rate, BCKAD/DA, LRCKAD/DA, DOUT1/2, and DIN1/2 are used. In the case of high-speed TDM format in dual rate, BCKDA, LRCKDA, and DIN1 are used. In the case of high-speed TDM format in quad rate, BCKDA, LRCKDA, and DIN1/2 are used. TDM format and high-speed TDM format are supported only at SCKI = 512 f_S, 256 f_S, 128 f_S, and f_BCK ≤ f_SCKI. The audio data formats are selected by MC/SCL/FMT in hardware control mode and registers 65 and 81 in software control mode. All data must be in binary twos complement, MSB first.

Figure 47 through Figure 53 show 10 audio interface data formats. Table 11 summarizes the applicable formats and describes the relationships among them and the respective restrictions with mode control.

Figure 47. Audio Data Format: 24-Bit I²S

Figure 48. Audio Data Format: 24-Bit Left-Justified

Figure 49. Audio Data Format: 24-Bit Right-Justified

Figure 50. Audio Data Format: 16-Bit Right-Justified

Figure 51. Audio Data Format: 24-Bit DSP Format

Figure 52. Audio Data Format: 24-Bit TDM Format (SCKI = 128 f_S, 256 f_S, and 512 f_S Only)

Figure 53. Audio Data Format: 24-Bit High-Speed TDM Format
(SCKI = 128 f_S, 256 f_S, DAC, and Slave Mode Only)

9.4.5 Synchronization With the Digital Audio System

The PCM3168A device operates under the system clock (SCKI) and the audio sampling rate (LRCKAD/DA). Therefore, SCKI and LRCKAD/DA must have a specific relationship in slave mode. The PCM3168A device does not need a specific phase relationship between the audio interface clocks (LRCKAD/DA, BCKAD/DA) and the system clock (SCKI), but does require a specific frequency relationship (ratiometric) between LRCKAD/DA, BCKAD/DA, and SCKI.

If the relationship between SCKI and LRCKDA changes more than ±2 BCKDA clocks because of jitter, sampling frequency change, and so forth, the DAC internal operation halts within 1 / f_S, and the analog output is forced into VCOMDA (0.5 VCCDA1) until re-synchronization between SCKI, LRCKDA, and BCKDA is completed and then t_DACDLY3 passes. If the relationship between SCKI and LRCKAD changes more than ±2 BCKADs because of jitter, sampling frequency change, and so forth, the ADC internal operation halts within 1 / f_S, and the digital output is forced into a 0 code until re-synchronization between SCKI, LRCKAD, and BCKAD is completed and then t_ADCDLY3 passes. In the event the change is less than ±2 BCKAD/DAs, re-synchronization does not occur, and this analog/digital output control and discontinuity do not occur.

Figure 7 shows the DAC analog output and ADC digital output for loss of synchronization. During undefined data periods, some noise may be generated in the audio signal. Also, the transition of normal to undefined data and undefined (or zero) data to normal data creates a discontinuity of data on the analog and digital outputs, which then may generate some noise in the audio signal.

Both ADC outputs (DOUTx) and DAC outputs (VOUTx) hold the previous state if the system clock halts, but the asynchronous and re-synchronization processes would occur after the system clock resumes. Figure 7 shows DAC outputs and ADC outputs for loss of synchronization.

Table 12. Register Map

9.5.1 Control Register Definitions (Software Mode Only)

The PCM3168A device has many user-programmable functions that are accessed through control registers, and is programmed through the SPI or I²C serial control port. Table 13 shows the available mode control functions along with reset default conditions and associated register address. Table 12 lists the register map.

9.5.2 Register Definitions