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ZHCSQM3 December 2022 OPT3005

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

DTS|8
- MPSS136D

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

zhcsqm3_oa

8.4.2.1 Latched Window-Style Comparison Mode

The latched window-style comparison mode is typically selected when using the OPT3005 to interrupt an external processor. In this mode, a fault is recognized when the input signal is above the high-limit register or below the low-limit register. When the consecutive fault events trigger the interrupt reporting mechanisms, these mechanisms are latched, thus reporting whether the fault is the result of a high or low comparison. These mechanisms remain latched until the configuration register is read, which clears the INT pin and flag high and flag low fields. The SMBus alert response protocol, described in detail in the SMBus Alert Response section, clears the pin but does not clear the flag high and flag low fields. The behavior of this mode, along with the conversion ready flag, is summarized in Table 8-2. Note that Table 8-2 does not apply when the two threshold low register MSBs (see the Transparent Hysteresis-Style Comparison Mode section for clarification on the MSBs) are set to 11b.

Table 8-2 Latched Window-Style Comparison Mode: Flag Setting and Clearing Summary⁽²⁾⁽⁴⁾

OPERATION	FLAG HIGH FIELD	FLAG LOW FIELD	INT PIN⁽¹⁾	CONVERSION READY FIELD
The result register is above the high-limit register for fault count times. See the Result Register and the High-Limit Register for further details.	1	X	Active	1
The result register is below the low-limit register for fault count times. See the Result Register and the Low-Limit Register for further details.	X	1	Active	1
The conversion is complete with fault count criterion not met	X	X	X	1
Configuration register read⁽³⁾	0	0	Inactive	0
Configuration register write, M[1:0] = 00b (shutdown)	X	X	X	X
Configuration register write, M[1:0] > 00b (not shutdown)	X	X	X	0
SMBus alert response protocol	X	X	Inactive	X

(1) The INT pin depends on the setting of the polarity field (POL). The INT pin is low when the pin state is active and POL = 0 (active low) or when the pin state is inactive and POL = 1 (active high).

(2) X = no change from the previous state.

(3) Immediately after the configuration register is read, the device automatically resets the conversion ready field to the 0 state. Thus, if two configuration register reads are performed immediately after a conversion completion, the first reads 1 and the second reads 0.

(4) The high-limit register is assumed to be greater than the low-limit register. If this assumption is incorrect, the flag high field and flag low field can take on different behaviors.