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ZHCSNP1A March 2021 – October 2021 MCT8316Z

PRODUCTION DATA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

RGF|40
- MPQF173F

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

RGF|40
- QFND672

訂購信息

8.3.16 Protections

The MCT8316Z family of devices is protected against VM undervoltage, charge pump undervoltage, and overcurrent events. Table 8-8 summarizes various faults details.

Table 8-8 Fault Action and Response (SPI Devices)

FAULT	CONDITION	CONFIGURATION	REPORT	H-BRIDGE	LOGIC	RECOVERY
VM undervoltage (NPOR)	V_VM < V_UVLO	—	—	Hi-Z	Disabled	Automatic: V_VM > V_{UVLO_R} CLR_FLT, nSLEEP Reset Pulse (NPOR bit)
AVDD undervoltage (NPOR)	V_AVDD < V_{AVDD_UV}	—	—	Hi-Z	Disabled	Automatic: V_AVDD > V_{AVDD_UV_R} CLR_FLT, nSLEEP Reset Pulse (NPOR bit)
Buck undervoltage (BUCK_UV)	V_{FB_BK} < V_{BK_UV}	—	nFAULT	Active	Active	Automatic: V_{FB_BK} > V_{BUCK_UV_R} CLR_FLT, nSLEEP Reset Pulse (BUCK_UV bit)
Charge pump undervoltage (VCP_UV)	V_CP < V_CPUV	—	nFAULT	Hi-Z	Active	Automatic: V_VCP > V_CPUV CLR_FLT, nSLEEP Reset Pulse (VCP_UV bit)
OverVoltage Protection (OVP)	V_VM > V_OVP	OVP_EN = 0b	None	Active	Active	No action (OVP Disabled)
OverVoltage Protection (OVP)	V_VM > V_OVP	OVP_EN = 1b	FAULT	Hi-Z	Active	Automatic: V_VM < V_OVP CLR_FLT, nSLEEP Reset Pulse (OVP bit)
Overcurrent Protection (OCP)	I_PHASE > I_OCP	OCP_MODE = 00b	nFAULT	Hi-Z	Active	Latched: CLR_FLT, nSLEEP Reset Pulse (OCP bits)
		OCP_MODE = 01b	nFAULT	Hi-Z	Active	Retry: t_RETRY
		OCP_MODE = 10b	nFAULT	Active	Active	Automatic: CLR_FLT, nSLEEP Reset Pulse (OCP bits)
		OCP_MODE = 11b	None	Active	Active	No action
Buck Overcurrent Protection (BUCK_OCP)	I_BK > I_{BK_OC}	—	nFAULT	Active	Active	Retry: t_RETRY
SPI Error (SPI_FLT)	SCLK fault and ADDR fault	SPI_FLT_REP = 0b	nFAULT	Active	Active	Automatic: CLR_FLT, nSLEEP Reset Pulse (SPI_FLT bit)
SPI Error (SPI_FLT)	SCLK fault and ADDR fault	SPI_FLT_REP = 1b	None	Active	Active	No action
OTP Error (OTP_ERR)	OTP reading is erroneous	—	nFAULT	Hi-Z	Active	Latched: Power Cycle, nSLEEP Reset Pulse
Motor Lock (MTR_LOCK)	No Hall Signals > t_{MTR_LOCK_TDET}	MTR_LOCK_MODE = 00b	nFAULT	Hi-Z	Active	Latched: CLR_FLT, nSLEEP Pulse (MTR_LOCK bit)
		MTR_LOCK_MODE = 01b	nFAULT	Hi-Z	Active	Retry: t_{MTR_LOCK_RETRY}
		MTR_LOCK_MODE = 10b	nFAULT	Active	Active	Automatic: CLR_FLT, nSLEEP Reset Pulse (OCP bits)
		MTR_LOCK_MODE = 11b	None	Active	Active	No action
Thermal warning (OTW)	T_J > T_OTW	OTW_REP = 0b	None	Active	Active	No action
Thermal warning (OTW)	T_J > T_OTW	OTW_REP = 1b	nFAULT	Active	Active	Automatic: T_J < T_OTW – T_HYS CLR_FLT, nSLEEP Pulse (OTW bit)
Thermal shutdown (OTSD)	T_J > T_OTSD	—	nFAULT	Hi-Z	Active	Automatic: T_J < T_OTSD – T_HYS CLR_FLT, nSLEEP Pulse (OTS bit)