ZHCSNP1A March 2021 – October 2021 MCT8316Z
PRODUCTION DATA
If at any time the voltage on VFB_BK pin falls lower than the VBK_UV threshold, the integrated FETs of the buck regulator are disabled while the driver FETs, charge pump, and digital logic control continue to operate normally. The nFAULT pin is driven low in the event of a buck undervoltage fault, and the BK_FLT bit in IC_STAT register is set in SPI devices. The FAULT and BUCK_UV bits are also latched high in the registers on SPI devices. Normal operation starts again (buck regulator operation and the nFAULT pin is released) when the BUCK undervoltage condition clears. The BK_FLT and BUCK_UV bits stay set until cleared through the CLR_FLT bit or an nSLEEP pin reset pulse (tRST).