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ZHCSRT4 august 2023 LV5144

PRODUCTION DATA

封裝選項

機械數據 (封裝 | 引腳)

RGY|20
- MPQF116H

散熱焊盤機械數據 (封裝 | 引腳)

RGY|20
- QFND755

訂購信息

zhcsrt4_oa

7.5 Electrical Characteristics

Typical values correspond to T_J = 25°C. Minimum and maximum limits apply over the –40°C to 150°C junction temperature range unless otherwise stated. V_VIN = 48 V, V_EN/UVLO = 1.5 V, R_RT = 25 kΩ unless otherwise stated

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT SUPPLY
V_IN	Operating input voltage range		6		95	V
I_Q-RUN	Operating input current, not switching	V_EN/UVLO = 1.5 V, V_SS/TRK = 0 V		2		mA
I_Q-STBY	Standby input current	V_EN/UVLO = 1 V		2		mA
I_Q-SHDN	Shutdown input current	V_EN/UVLO = 0 V, V_VCC < 1 V		20		μA
VCC REGULATOR
V_VCC	VCC regulation voltage	V_SS/TRK = 0 V, 9 V < V_VIN < 48 V, 0 mA < I_VCC < 20 mA		7.5		V
V_VCC-LDO	VIN to VCC dropout voltage	V_VIN = 6 V, V_SS/TRK = 0 V, I_VCC = 20 mA		0.25	0.72	V
I_SC-LDO	VCC short-circuit current	V_SS/TRK = 0 V, V_VCC = 0 V	40	50	70	mA
V_VCC-UV	VCC undervoltage threshold	VCC rising	4.8	4.93	5.2	V
V_VCC-UVH	VCC undervoltage hysteresis	Rising threshold – falling threshold		0.26		V
V_VCC-EXT	Minimum external bias voltage	Voltage required to disable VCC regulator	8			V
I_VCC	External VCC input current, not switching	V_SS/TRK = 0 V, V_VCC = 13 V			2.3	mA
ENABLE AND INPUT UVLO
V_SHDN	Shutdown to standby threshold	V_EN/UVLO rising		0.42		V
V_SHDN-HYS	Shutdown threshold hysteresis	EN/UVLO Rising threshold – falling threshold		50		mV
V_EN	Standby to operating threshold	V_EN/UVLO rising	1.164	1.2	1.236	V
I_EN-HYS	Standby to operating hysteresis current	V_EN/UVLO = 1.5 V	9	10	11	μA
ERROR AMPLIFIER
V_REF	FB reference Voltage	FB connected to COMP	792	800	808	mV
I_FB-BIAS	FB input bias current	V_FB = 0.8 V, -40℃ to +125℃	–100		100	nA
I_FB-BIAS	FB input bias current	V_FB=0.8 V, T_J= +150℃	–200		200	nA
V_COMP-OH	COMP output high voltage	V_FB = 0 V, COMP sourcing 1 mA		5		V
V_COMP-OL	COMP output low voltage	COMP sinking 1 mA			0.3	V
AVOL	DC gain			94		dB
GBW	Unity gain bandwidth			6.5		MHz
SOFT-STARTand VOLTAGE TRACKING
I_SS	SS/TRK capacitor charging current	V_SS/TRK = 0 V	8.5	10	12	μA
R_SS	SS/TRK discharge FET resistance	V_EN/UVLO = 1 V, V_SS/TRK = 0.1 V		11		Ω
V_SS-FB	SS/TRK to FB offset	V_SS/TRK – V_FB, V_FB = 0.8 V	–15	0	15	mV
V_SS-CLAMP	SS/TRK clamp voltage	V_FB = 0.8 V		0.115		V
POWER GOOD INDICATOR
PG_UTH	FB upper threshold for PGOOD high to low	% of V_REF, V_FB rising		108		%
PG_LTH	FB lower threshold for PGOOD high to low	% of V_REF, V_FB falling		92		%
PG_{HYS_U}	PGOOD upper theshold hysteresis	% of V_REF		3		%
PG_{HYS_L}	PGOOD lower threshold hysteresis	% of V_REF		2		%
T_PG-RISE	PGOOD rising filter	FB to PGOOD rising edge		25		us
T_PG-FALL	PGOOD falling filter	FB to PGOOD falling edge		25		us
V_PG-OL	PGOOD low state output voltage	V_FB = 0.9 V, I_PGOOD = 2 mA			150	mV
I_PG-OH	PGOOD high state leakage current	V_FB = 0.8 V, V_PGOOD = 13 V, -40℃ to +150℃			400	nA
I_PG-OH	PGOOD high state leakage current	V_FB = 0.8 V, V_PGOOD = 13 V			400	nA
OSCILLATOR
F_SW1	Oscilator frequency – 1	R_RT = 100 kΩ		100		kHz
F_SW2	Oscillator frequency – 2	R_RT = 25 kΩ		400		kHz
F_SW3	Oscillator frequency – 3	R_RT = 12.5 kΩ		780		kHz
SYNCHRONIZATION INPUT AND OUTPUT
F_SYNC	SYNCIN external clock frequency range	% of nominal frequency set by R_RT	–20		50	%
V_SYNC-IH	SYNCIN input logic high		2			V
V_SYNC-IL	SYNCIN input logic low				0.8	V
R_SYNC-IN	SYNCIN input resistance	V_SYNCIN = 3 V		20		kΩ
T_SYNCI-PW	SYNCIN input minimum pulsewidth	Minimum high state or low state duration	50			ns
V_SYNCO-OH	SYNCOUT high-state output voltage	I_SYNCOUT = –1 mA (sourcing current)	3			V
V_SYNCO-OL	SYNCOUT low-state output voltage	I_SYNCOUT = 1 mA (sinking current)			0.4	V
T_SYNCOUT	Delay from HO rising to SYNCOUT leading edge	V_SYNCIN = 0 V, T_S = 1/F_SW, F_SW set by R_RT		T_S/2 – 140		ns
T_SYNCIN	Delay from SYNCIN rising to HO leading edge	50% to 50%		150		ns
GATE DRIVERS
R_HO-UP	HO high state resistance, HO to BST	V_BST – V_SW = 7 V, I_HO = –100 mA		1.5		Ω
R_HO-DOWN	HO low state resistance, HO to SW	V_BST – V_SW = 7 V, I_HO = 100 mA		0.9		Ω
R_LO-UP	LO high state resistance, LO to VCC	V_BST – V_SW = 7 V, I_LO = –100 mA		1.5		Ω
R_LO-DOWN	LO low state resistance, LO to PGND	V_BST – V_SW = 7 V, I_LO = 100 mA		0.9		Ω
I_HOH, I_LOH	HO, LO source current	V_BST – V_SW = 7 V, HO = SW, LO = AGND		2.3		A
I_HOL, I_LOL	HO, LO sink current	V_BST – V_SW = 7 V, HO = BST, LO = VCC		3.5		A
T_HO-TR, T_LO-TR	HO, LO rise times	V_BST – V_SW = 7 V, C_LOAD = 1 nF, 20% to 80%		7		ns
T_HO-TF, T_LO-TF	HO, LO fall times	V_BST – V_SW = 7 V, C_LOAD = 1 nF, 80% to 20%		4		ns
T_HO-DT	HO turn-on deadtime	V_BST – V_SW = 7 V, 50% to 50%		14		ns
T_LO-DT	LO turn-on deadtime	V_BST – V_SW = 7 V, 50% to 50%		14		ns
BOOTSTRAP DIODE AND UNDER-VOLTAGE THRESHOLD
V_BST-FWD	VCC to BST	VCC to BST, BST pin sourcing 20 mA		0.75	0.9	V
I_Q-BST	BST to SW quiescent current, not switching	V_SS/TRK = 0 V, V_SW = 48 V, V_BST = 54 V		80		μA
V_BST-UV	BST to SW undervoltage detection	V_BST – V_SW falling		3.4		V
V_BST-HYS	BST to SW undervoltage hysteresis	V_BST – V_SW rising		0.42		V
PWM CONTROL
T_ON(min)	Minimum controllable on-time	V_BST – V_SW = 7 V, HO 50% to 50%		45		ns
T_OFF(min)	Minimum off-time	V_BST – V_SW = 7 V, HO 50% to 50%		145		ns
DC_100KHz	Maximum duty cycle	F_SW = 100 kHz, 5.5 V < V_VIN < 60 V	98	99		%
DC_400kHz		F_SW = 400 kHz, 5.5 V < V_VIN < 60 V	90	94		%
V_RAMP(min)	RAMP valley voltage (COMP at 0% duty cycle)			300		mV
k_FF	PWM feedforward gain (V_IN / V_RAMP)	5.5 V < V_VIN < 100 V		15		V / V
OVER CURRENT PROTECT (OCP) - VALLEY CURRENT LIMITING
I_RS	ILIM source current, R_SENSE Mode	Low voltage detected at ILIM		100		μA
I_RDSON	ILIM source current, R_DS-ON mode	SW voltage detected at ILIM , T_J = 25°C	180	200	220	μA
I_RSTC	ILIM current tempco	R_DS-ON mode		4500		ppm/°C
I_RDSONTC	ILIM current tempco	R_SENSE mode		0		ppm/°C
V_ILIM-TH	ILIM comparator threshold at ILIM		–8	–2	3.5	mV
SHORT CIRCUIT PROTECTION (SCP) - DUTY CYCLE CLAMP
V_CLAMP-OS	Clamp offset voltage - No current limiting	COMP to duty cycle clamp voltage		0.2 + V_VIN/75		V
V_CLAMP-MIN	Minimum duty cycle clamp voltage	Clamp voltage with continuous OCP		0.3 + V_VIN/150		V
HICCUP MODE FAULT PROTECTION
C_HICC-DEL	Hiccup mode activation delay	Clock cycles with current limiting before off-time activated		128		cycles
C_HICCUP	Hiccup mode off time after activation	Clock cycles with no switching followed by SS/TRK release		8192		cycles
DIODE EMULATION / DCM OPERATION
V_ZCD-SS	Zero-cross detect (ZCD) soft-start ramp	ZCD threshold measured at SW pin 50 cycles after first HO pulse		0		mV
V_ZCD-DIS	Zero-cross detect disable threshold	ZCD threshold measured at SW pin 1000 cycles after first HO pulse		200		mV
V_DEM-TH	Diode emulation zero-cross threshold	Measured at SW with V_SW rising		0		mV
THERMAL SHUTDOWN
T_SD	Thermal shutdown threshold	T_J rising		175		°C
T_SD-HYS	Thermal shutdown hysteresis			20		°C
Switching Characteristics
T_HO-TR,T_LO-TR	HO, LO rise times	V_BST-V_SW=7 V, C_LOAD=1 nF, 20% to 80%		7		ns
T_HO-TF, T_LO-TF	HO, fall times	V_BST-V_SW=7 V, C_LOAD=1 nF, 20% to 80%		4		ns
T_HO-DT	HO turnon dead time	V_BST- V_SW=7 V, LO off to HO on, 50% to 50%		14		ns