ZHCSR22A June 2021 – September 2022 LP876242-Q1
PRODUCTION DATA
When the device arrives at a mission state, all rail sequencing is controlled by the pre-configurable FSM engine (PFSM) through the configuration memory. The configuration memory allows configurations of the triggers and the operation states that together form the configurable sub state machine within the scope of mission states. This sub state machine can be used to control and sequence the different voltage outputs as well as any GPIO outputs that can be used as enable for external rails. When the device is in a mission state, it has the capacity to supply the processor and other platform modules depending on the power rail configuration. The definitions and transition triggers of the mission states are configurable through the NVM configuration. Unlike the user registers, the PFSM definition stored in the NVM cannot be modified during normal operation. When the PMIC determines that a transition to another operation state is necessary, it reads the configuration memory to determine what sequencing is needed for the state transition.
Table 7-11 shows how the trigger signals for each state transition can come from a variety of interface or GPIO inputs, or potential error sources. Figure 7-36 shows how the device processes all of the possible error sources inside the PFSM engine, a hierarchical mask system is applied to filter out the common errors that can be handled by interrupt only, and categorize the other error sources as Severe Global Error, Moderate Global Error, and so forth. The filtered and categorized triggers are sent into the PFSM engine, that then determines the entry and exit condition for each configured mission state.
Figure 7-38 shows an example of how the PFSM engine utilizes instructions to execute the configured device state and sequence transitions of the mission state-machine. Table 7-8 provides the instruction set and usage description of each instruction in the following sections. Section 7.4.1.2.2 describes how the instructions are stored in the NVM memory.
| Command Opcode | Command | Command Description |
|---|---|---|
| "0000" | REG_WRITE_MASK_PAGE0_IMM | Write the specified data, except the masked bits, to the specified page 0 register address. |
| "0001" | REG_WRITE_IMM | Write the specified data to the specified register address. |
| "0010" | REG_WRITE_MASK_IMM | Write the specified data, except the masked bits, to the specified register address. |
| "0011" | REG_WRITE_VOUT_IMM | Write the target voltage of a specified regulator after a specified delay. |
| "0100" | REG_WRITE_VCTRL_IMM | Write the operation mode of a specified regulator after a specified delay. |
| "0101" | REG_WRITE_MASK_SREG | Write the data from a scratch register, except the masked bits, to the specified register address. |
| "0110" | SREG_READ_REG | Write scratch register (REG0-3) with data from a specified address. |
| "0111" | WAIT | Execution is paused until the specified type of the condition is met or timed out. |
| "1000" | DELAY_IMM | Delay the execution by a specified time. |
| "1001" | DELAY_SREG | Delay the execution by a time value stored in the specified scratch register. |
| "1010" | TRIG_SET | Set a trigger destination address for a given input signal or condition. |
| "1011" | TRIG_MASK | Sets a trigger mask that determines which triggers are active. |
| "1100" | END | Mark the final instruction in a sequential task. |
| "1101" | REG_WRITE_BIT_PAGE0_IMM | Write the specified data to the BIT_SEL location of the specified page 0 register address. |
| "1110" | REG_WRITE_WIN_PAGE0_IMM | Write the specified data to the SHIFT location of the specified page 0 register address. |
| "1111" | SREG_WRITE_IMM | Write the specified data to the scratch register (REG0-3). |