When the device releases the nRSTOUT pin, the watchdog starts with the Long Window. This Long Window has a time interval (t_{LONG_WINDOW}) with a default value set in bits WD_LONGWIN[7:0].

As long as the watchdog is in the Long Window, the MCU can configure the watchdog through the following register bits:

• WD_EN to enable or disable the watchdog
• WD_LONGWIN[7:0] to increase the duration of the Long-Window time-interval
• WD_MODE_SELECT to select the Watchdog mode (Trigger mode or Q&A Mode)
• WD_PWRHOLD to activate the Watchdog Disable function (more detail in Section 7.3.8.4)
• WD_RETURN_LONGWIN to configure whether to return to Long-Window or continue to the next sequence after the completion of the current watchdog sequence (more detail in Section 7.3.8.4)
• WD_WIN1[6:0] to configure the duration of the Window-1 time-interval
• WD_WIN2[6:0] to configure the duration of the Window-2 time-interval
• WD_RST_EN to enable or disable the watchdog-reset function
• WD_FAIL_TH[2:0] to configure the Watchdog-Fail threshold
• WD_RST_TH[2:0] to configure the Watchdog-Reset threshold
• WD_QA_FDBK[1:0] to configure the settings for the reference answer-generation
• WD_QA_LFSR[1:0] to configure the settings for the question-generation
• WD_QUESTION_SEED[3:0] to configure the starting-point for the 1st question-generation

The device keeps the above register bit values configured by the MCU as long as the device is powered.

The MCU can configure the time interval of the Long Window (t_{LONG_WINDOW}) with the WD_LONGWIN[7:0] bits. The WD_LONGWIN[7:0] bits are defined as:

• 0x00: 80 ms
• 0x01 - 0x40: 125 ms to 8 sec, in 125-ms steps
• 0x41 - 0xFF: 12 sec to 772 sec, in 4-sec steps

Use Equation 5 and Equation 6 to calculate the minimum and maximum values for the Long Window (t_{LONG_WINDOW}) time interval when WD_LONGWIN[7:0] > 0x00:

When the MCU clears bit WD_EN, the watchdog goes out of the Long Window and disables the watchdog. When the watchdog is disabled in this way, the MCU can set bit WD_EN back to ‘1’ to enable the watchdog again, and the MCU can control the ENABLE_DRV bit when no other error-flags are set. The MCU must clear bit WD_PWRHOLD before setting bit WD_EN back to ‘1’ to start the watchdog in Long Window.

The watchdog locks the following configuration register bits when it goes out of the Long Window and starts the first watchdog sequence:

• WD_WIN1[6:0]
• WD_WIN2[6:0]
• WD_LONGWIN[7:0]
• WD_MODE_SELECT
• WD_QA_FDBK[1:0], WD_QA_LFSR[1:0] and WD_QUESTION_SEED[3:0]
• WD_RST_EN, WD_EN, WD_FAIL_TH[2:0] and WD_RST_TH[2:0]