ZHCSET9B January 2016 – June 2018 LP8758-E0
PRODUCTION DATA.
Address: 0x18
| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
| INT_BUCK3 | INT_BUCK2 | INT_BUCK1 | INT_BUCK0 | TDIE_SD | TDIE_WARN | RESET_REG | I_LOAD_
READY |
| Bits | Field | Type | Default | Description |
|---|---|---|---|---|
| 7 | INT_BUCK3 | R | 0 | Interrupt indicating that output BUCK3 has a pending interrupt. The reason for the interrupt is indicated in INT_BUCK3 register.
This bit is cleared automatically when INT_BUCK3 register is cleared to 0x00. |
| 6 | INT_BUCK2 | R | 0 | Interrupt indicating that output BUCK2 has a pending interrupt. The reason for the interrupt is indicated in INT_BUCK2 register.
This bit is cleared automatically when INT_BUCK2 register is cleared to 0x00. |
| 5 | INT_BUCK1 | R | 0 | Interrupt indicating that output BUCK1 has a pending interrupt. The reason for the interrupt is indicated in INT_BUCK1 register.
This bit is cleared automatically when INT_BUCK1 register is cleared to 0x00. |
| 4 | INT_BUCK0 | R | 0 | Interrupt indicating that output BUCK0 has a pending interrupt. The reason for the interrupt is indicated in INT_BUCK0 register.
This bit is cleared automatically when INT_BUCK0 register is cleared to 0x00. |
| 3 | TDIE_SD | R/W | 0 | Latched status bit indicating that the die junction temperature has exceeded the thermal shutdown level. The converter cores have been disabled if they were enabled. The converter cores cannot be enabled if this bit is active. The actual status of the thermal warning is indicated by TOP_STAT.TDIE_SD_STAT bit.
Write 1 to clear interrupt. |
| 2 | TDIE_WARN | R/W | 0 | Latched status bit indicating that the die junction temperature has exceeded the thermal warning level. The actual status of the thermal warning is indicated by TOP_STAT.TDIE_WARN_STAT bit.
Write 1 to clear interrupt. |
| 1 | RESET_REG | R/W | 0 | Latched status bit indicating that either startup (NRST rising edge) has done, VANA supply voltage has been below undervoltage threshold level or the host has requested a reset (RESET.SW_RESET). The converter cores have been disabled, and registers are reset to default values and the normal startup procedure is done.
Write 1 to clear interrupt. |
| 0 | I_LOAD_READY | R/W | 0 | Latched status bit indicating that the load current measurement result is available in I_LOAD_1 and I_LOAD_2 registers.
Write 1 to clear interrupt. |