ZHCSD11D September 2014 – December 2018 LP5907-Q1
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
The dynamic performance of the LP5907-Q1 is dependant on the layout of the PCB. PCB layout practices that are adequate for typical LDOs may degrade the PSRR, noise, or transient performance of the LP5907-Q1.
Best performance is achieved by placing CIN and COUT on the same side of the PCB as the LP5907-Q1, and as close as is practical to the package. The ground connections for CIN and COUT must be back to the LP5907-Q1 ground pin using as wide and short copper traces as are practical.
Avoid connections using long trace lengths, narrow trace widths, and/or connections through vias. These add parasitic inductances and resistance that results in inferior performance especially during transient conditions