ZHCSIY5A October 2018 – May 2019 LMZM33604
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Adjusting the Output Voltage
- 7.3.2 Input Capacitor Selection
- 7.3.3 Output Capacitor Selection
- 7.3.4 Transient Response
- 7.3.5 Feed-Forward Capacitor
- 7.3.6 Switching Frequency (RT)
- 7.3.7 Synchronization (SYNC/MODE)
- 7.3.8 Output Enable (EN)
- 7.3.9 Programmable System UVLO (EN)
- 7.3.10 Internal LDO and BIAS_SEL
- 7.3.11 Power Good (PGOOD) and Power Good Pullup (PGOOD_PU)
- 7.3.12 Mode Select (Auto or FPWM)
- 7.3.13 Soft Start and Voltage Tracking
- 7.3.14 Voltage Dropout
- 7.3.15 Overcurrent Protection (OCP)
- 7.3.16 Thermal Shutdown
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.3.9 Programmable System UVLO (EN)
Many applications benefit from employing an enable divider to establish a customized system UVLO. This can be used for sequencing, to satify a system timing requirement, or to reduce the occurrence of deep discharge of a battery power source. Figure 35 shows how to use a resistor divider to set a system UVLO level. An external logic output can also be used to drive the EN pin for system sequencing.
Figure 35. System UVLO Table 7 lists recommended resistor values for RENT and RENB to adjust the system UVLO voltage. TI recommends to set the system UVLO turn-on threshold to approximately 80% to 85% of the minimum expected input voltage.
Table 7. Resistor Values for Setting System UVLO
| UVLO (V) | 6.5 | 10 | 15 | 20 | 25 |
|---|---|---|---|---|---|
| RENT (kΩ) | 100 | 100 | 100 | 100 | 100 |
| RENB (kΩ) | 22.6 | 13.7 | 8.66 | 6.34 | 4.99 |