ZHCSHO0C February 2018 – March 2023 LMZM23600
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| FEEDBACK | ||||||
| VFB | Initial output voltage accuracy (3.3-V and 5-V fixed output) | VIN = 4 V to 36 V, open loop | –1.5% | 1.5% | ||
| VFB | Reference voltage (ADJ option) | VIN = 4 V to 36 V, open loop | 0.985 | 1 | 1.015 | V |
| IFB | Input current from FB to GND (ADJ option) | FB = 1 V | 20 | nA | ||
| CURRENT | ||||||
| IQ | Operating quiescent current; measured at VIN pin | VIN = 12 V, VFB = +10%, VOUT = 5 V | 7 | μA | ||
| VIN = 12 V, VFB = +10%, VOUT = 5 V, TJ = 85°C | 16 | μA | ||||
| VIN = 12 V, VFB = +10%, VOUT = 5 V, TJ = 125°C | 18 | |||||
| VIN = 24 V, VFB = +10%, VOUT = 5 V | 12 | |||||
| VIN = 24 V, VFB = +10%, VOUT = 5 V, TJ = 85°C | 24 | |||||
| VIN = 24 V, VFB = +10%, VOUT = 5 V, TJ = 125°C | 26 | |||||
| IB | Bias current into the VOUT pin | VIN = 24 V, VFB = +10%, VOUT = 5 V, Mode = 0 V | 48 | 80 | μA | |
| ISD | Shutdown quiescent current; measured at VIN pin | EN = 0 V, VIN = 12 V, TJ = 25°C | 1.8 | μA | ||
| EN = 0 V, VIN = 12 V, TJ = 85°C | 3 | |||||
| EN = 0 V, VIN = 24 V, TJ = 25°C | 5 | |||||
| EN = 0 V, VIN = 24 V, TJ = 85°C | 10 | |||||
| UNDERVOLTAGE LOCKOUT (UVLO) | ||||||
| VIN_UVLO | Minimum input voltage to operate | Rising | 3.1 | 3.5 | 3.85 | V |
| VIN_UVLO_HYST | UVLO hysteresis | 0.2 | 0.25 | 0.3 | V | |
| POWER GOOD FLAG (PGOOD) | ||||||
| VPGOOD_OV | PGOOD upper threshold voltage | Rising, % of Vout | 103.5% | 106.7% | 109% | |
| VPGOOD_UV | PGOOD lower threshold voltage | Falling, % of Vout | 92% | 94.7% | 97% | |
| VPGOOD_GUARD | Magnitude of PGOOD lower threshold difference from steady state output voltage. | Steady state output voltage PGOOD threshold read at the same TJ and VIN | 4% | |||
| VPGOOD_HYST | PGOOD hysteresis as a percent of output voltage set point | 1.4% | ||||
| VPGOOD_VALID | Minimum input voltage for proper PGOOD function | 50-μA pullup to PGOOD pin, EN = 0 V, TJ = 25°C | 1.0 | 1.5 | V | |
| tRESET_FILTER | Glitch filter time constant for PGOOD function | 190 | μs | |||
| VOL | Low-level PGOOD function output voltage | 50-μA pullup to PGOOD pin, VIN = 1.5 V, EN = 0 V | 0.4 | V | ||
| 0.5-mA pullup to PGOOD pin, VIN = 12 V, EN = 0 V | 0.4 | |||||
| 1-mA pullup to PGOOD pin, VIN = 12 V, EN = 3.3 V | 0.4 | |||||
| RPGOOD_RDSON | RDSON of the PGOOD output pull down | 50 | 110 | Ω | ||
| SWITCHING FREQUENCY | ||||||
| fSW | Switching frequency | VIN = 24 V, 5-V and 3.3-V fixed output options | 675 | 750 | 825 | kHz |
| VIN = 24 V, ADJ output options | 890 | 1000 | 1090 | |||
| VIN = 36 V, 5-V and 3.3-V fixed output options | 750 | |||||
| VIN = 36 V, ADJ output options | 800 | |||||
| FREQUENCY SYNCHRONIZATION AND MODE | ||||||
| fSYNC | Sync frequency range | 5-V and 3.3-V fixed output options VOUT + VDROPOUT < VIN < 36 V | 500 | 825 | kHz | |
| ADJ output options VOUT + VDROPOUT< VIN < 28 V | 700 | 1100 | ||||
| DSYNC | Sync input duty cycle range | 2.3 V < HIGH state input < 5.5 V | 25% | 75% | ||
| VMODE_HIGH | MODE/SYNC input logic HIGH voltage to enter FPWM mode | 1.5 | V | |||
| VMODE_LOW | MODE/SYNC input logic LOW voltage to enter AUTO PFM mode | 0.4 | V | |||
| IMODE | MODE/SYNC leakage current | VIN = 12 V, VMODE/SYNC = 3.3 V | 1 | μA | ||
| VIN = 12 V, VMODE/SYNC = 12V | 5 | |||||
| tMODE | MODE transition time to FPWM | VIN = 12 V, VOUT = 5 V, IOUT= 20 mA | 300 | μs | ||
| MODE transition time to AUTO PFM | VIN = 12 V, VOUT = 5 V, IOUT = 20 mA | 300 | ||||
| CURRENT LIMIT PROTECTION | ||||||
| IL-HS | 0.5-A option high-side switch current limit | Duty cycle approaches 0% | 0.94 | 1.35 | 1.6 | A |
| IL-LS | 0.5-A option low-side switch current limit | 0.5 | 0.625 | 0.75 | A | |
| IL-ZC | Zero-cross current limit | MODE/SYNC = logic LOW | –0.01 | A | ||
| IL-NEG | Low-side reverse current limit (positive current ino the SW pin to GND) | MODE/SYNC = logic HIGH | 0.5 | 0.8 | A | |
| POWER STAGE CHARACTERISTICS | ||||||
| HS RDS-ON | High-side MOSFET on-resistance | 220 | mΩ | |||
| LS RDS-ON | Low-side MOSFET on-resistance | 200 | mΩ | |||
| tON-MIN | Minimum high-side on-time | IOUT = 500 mA | 50 | 80 | ns | |
| tOFF-MIN | Minimum high-side off-time | IOUT = 500 mA, ADJ | 62 | 100 | ns | |
| DMAX | Maximum switch duty cycle | 5-V and 3.3-V fixed output options | 93% | |||
| ADJ option | 91% | |||||
| While in frequency foldback | 97% | |||||
| L | Integrated inductor - inductance | 10 | μH | |||
| LDCR | Integrated inductor - DCR | 390 | mΩ | |||
| ENABLE | ||||||
| VEN | Enable input threshold voltage | Rising | 1.7 | 1.92 | V | |
| VEN_HYST | Enable input threshold hysteresis | 0.42 | 0.52 | V | ||
| VEN_WAKE | Enable input wake-up threshold | 0.4 | V | |||
| IEN | Enable pin input current | VIN = VEN = 12 V | 2.7 | μA | ||
| VCC REGULATOR | ||||||
| VCC | Internal VCC voltage | VIN = 12 V, VOUT < 3.3 V | 3.05 | V | ||
| VIN = 12 V, VOUT ≥ 3.3V | 3.15 | |||||
| VCC_UVLO | Internal VCC voltage input UVLO | VIN rising | 2.23 | 2.73 | 3.25 | V |
| VCC_UVLO_HYST | Internal VCC voltage input UVLO hysteresis | Hysteresis below VCC_UVLO | 150 | 240 | mV | |
| SOFT START | ||||||
| tSS | Soft-start time | Time for VREF to ramp from 0% to 90% | 1.8 | 3.5 | 5.5 | ms |
| tEN_LV | Turnon delay with low VIN | VIN < 4.2 V | 4 | ms | ||
| tEN | Turnon delay | VIN = 12 V | 0.7 | ms | ||
| tW | Short circuit wait time (hiccup time) | 8.0 | ms | |||
| THERMAL PROTECTION | ||||||
| TSD | Thermal shutdown | Rising threshold | 155 | °C | ||
| TSD_HYST | Thermal shutdown hysteresis | 15 | °C | |||