10.1 Layout Guidelines

PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules.

• Minimize area of switched current loops. Wehn considering EMI reduction, it is imperative to minimize the high di/dt paths during PC board layout. The high-current loops that do not overlap have high di/dt content that cause observable high frequency noise on the output pin if the input capacitor (C_IN1) is placed at a distance away from the LMZ14202. Therefore place C_IN1 as close as possible to the LMZ14202 VIN and GND exposed thermal pad. This placement minimizes the high di/dt area and reduce radiated EMI. Additionally, ensure that grounding for both the input and output capacitor consists of a localized top side plane that connects to the GND exposed thermal pad (EP).
• Have a single point ground. Route the ground connections for the feedback, soft-start, and enable components to the GND pin of the device. This routing prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior. Provide the single point ground connection from pin 4 to the exposed thremal pad.
• Minimize trace length to the FB pin. Place both feedback resistors, R_FBT and R_FBB, and the feed forward capacitor C_FF, close to the FB pin. Because the FB node is high impedance, maintain the copper area as small as possible. To minimize noise, route the traces from R_FBT, R_FBB, and C_FF away from the body of the LMZ14202 device.
• Make input and output bus connections as wide as possible. Width reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load to correct for voltage drops and provide optimum output accuracy.
• Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to inner layer heat-spreading ground planes. For best results use a 6 × 6 via array with minimum via diameter of 10 mils (254 μm) thermal vias spaced 59 mils (1.5 mm). Ensure enough copper area is used for heat-sinking to maintain the junction temperature below 125°C.

10.2 Layout Example

Figure 38. Minimize Area of Current Loops in Buck Module

Figure 39. PCB Layout Guide

Figure 40. EVM Board Layout - Top View

Figure 41. EVM Board Layout - Bottom View

10.3 Power Dissipation and Board Thermal Requirements

When V_IN = 24 V, V_O = 3.3 V, I_O = 2 A, T_A(max) = 85°C , and T_J = 125°C, the device must achieve a thermal resistance from case-to-ambient described by Equation 18.

Given the typical thermal resistance from junction to case to be 1.9 °C/W, use the 85°C power dissipation curves in Typical Characteristics to estimate the P_IC-LOSS for the application. In this application it is 1.5 W.

To reach R_θCA = 24.8, the PCB is required to dissipate heat effectively. With no airflow and no external heat, use Equation 20 to estimate the required board area covered by 1 oz. copper on both the top and bottom metal layers.

As a result, approximately 20.2 square cm of 1 oz copper on top and bottom layers is required for the PCB design. The PCB copper heat sink must be connected to the exposed pad. Approximately thirty-six, 10 mils (254 μm) thermal vias spaced 59 mils (1.5 mm) apart must connect the top copper to the bottom copper. For an example of a high thermal performance PCB layout, refer to the AN-2024 LMZ1420x / LMZ1200x Evaluation Board (SNVA422) .

10.4 Power Module SMT Guidelines

The recommendations below are for a standard module surface mount assembly

• Land Pattern Follow the PCB land pattern with either soldermask defined or non-soldermask defined pads
• Stencil Aperture
  • For the exposed die attach pad (DAP), adjust the stencil for approximately 80% coverage of the PCB land pattern
  • For all other I/O pads use a 1:1 ratio between the aperture and the land pattern recommendation
• Solder Paste Use a standard SAC Alloy such as SAC 305, type 3 or higher
• Stencil Thickness: 0.125 to 0.15 mm
• Reflow: Refer to solder paste supplier recommendation and optimized per board size and density
  • Refer to AN SNAA214 for reflow information
  • Maximum number of reflows allowed is one

Figure 42. Sample Reflow Profile