8.2.2.1.1 Enable Divider, R_ENT and R_ENB Selection

The enable input provides a precise, 1.18-V band-gap rising threshold to allow direct logic drive or connection to a voltage divider from a higher enable voltage such as V_IN. The enable input also incorporates 90 mV (typical) of hysteresis resulting in a falling threshold of 1.09 V. The maximum recommended voltage into the EN pin is 6.5 V. For applications where the midpoint of the enable divider exceeds 6.5 V, a small Zener diode can be added to limit this voltage.

The function of this resistive divider is to allow the designer to choose an input voltage below which the circuit becomes disabled. This implements the feature of programmable undervoltage lockout. This is often used in battery powered systems to prevent deep discharge of the system battery. It is also useful in system designs for sequencing of output rails or to prevent early turnon of the supply as the main input voltage rail rises at power-up. Applying the enable divider to the main input rail is often done in the case of higher input voltage systems such as 24-V AC/DC systems where a lower boundary of operation must be established. In the case of sequencing supplies, the divider is connected to a rail that becomes active earlier in the power-up cycle than the LMZ14202 output rail. Choose the two resistors based on Equation 1.

The LMZ14202 demonstration and evaluation boards use 11.8 kΩ for R_ENB and 68.1 kΩ for R_ENT resulting in a rising UVLO of 8 V. This divider presents 6.25 V to the EN input when the divider input is raised to 42 V.

The EN pin is internally pulled up to VIN and can be left floating for always-on operation.

8.2.2.1.2 Output Voltage Selection

Output voltage is determined by a divider of two resistors connected between V_O and ground. The midpoint of the divider is connected to the FB input. The voltage at FB is compared to a 0.8-V internal reference. In normal operation an ON-time cycle is initiated when the voltage on the FB pin falls below 0.8 V. The main MOSFET ON-time cycle causes the output voltage to rise and the voltage at the FB to exceed 0.8 V. As long as the voltage at FB is above 0.8 V, ON-time cycles does not occur.

The regulated output voltage determined by the external divider resistors R_FBT and R_FBB is:

Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:

Choose these resistors from values between 1 kΩ and 10 kΩ.

For V_O = 0.8 V the FB pin can be connected to the output directly so long as an output preload resistor remains that draws more than 20 µA. Converter operation requires this minimum load to create a small inductor ripple current and maintain proper regulation when no load is present.

A feed-forward capacitor is placed in parallel with R_FBT to improve load step transient response. Its value is usually determined experimentally by load stepping between DCM and CCM conduction modes and adjusting for best transient response and minimum output ripple.

A table of values for R_FBT , R_FBB , C_FF and R_DS(on) is included in the applications schematic.

8.2.2.1.3 Soft-Start Capacitor Selection

Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time to prevent overshoot.

Upon turnon, after all UVLO conditions have been passed, an internal 8 µA current source begins charging the external soft-start capacitor. The soft-start time duration to reach steady state operation is given by the formula:

This equation can be rearranged as follows:

Use of a 0.022-μF capacitor results in 2.2-ms soft-start duration which is recommended as a minimum value.

As the soft-start input exceeds 0.8 V the output of the power stage comes into regulation. The soft-start capacitor continues charging until it reaches approximately 3.8 V on the SS pin. Voltage levels between 0.8 V and 3.8 V have no effect on other circuit operation. The following conditions reset the soft-start capacitor by discharging the SS input to ground with an internal 200-μA current sink.

• The enable input being pulled low
• Thermal shutdown condition
• Over-current fault
• Internal V_CC UVLO (approximately 4-V input to V_IN)

8.2.2.1.4 C_O Selection

None of the required C_O output capacitance is contained within the module. At a minimum, the output capacitor must meet the worst-case minimum ripple current rating of 0.5 × I_LR(P-P), as calculated in Equation 17 below. Beyond the worst-case minimum, additional capacitance reduces output ripple as long as the ESR is low enough to permit it. A minimum value of 10 μF is generally required. Expect to experiment when designing an application to operate with a minimum value. Ceramic capacitors or other low ESR types are recommended. See AN-2024 LMZ1420x / LMZ1200x Evaluation Board (SNVA422) for more detail.

Equation 6 provides a good first-pass approximation of C_O for load transient requirements:

Solving:

The LMZ14202 demonstration and evaluation boards are populated with a 100-µF 6.3-V X5R output capacitor. Locations for extra output capacitors are provided. See See AN-2024 LMZ1420x / LMZ1200x Evaluation Board (SNVA422) for locations.

8.2.2.1.5 Input Capacitance (C_IN) Selection

The LMZ14202 module contains an internal 0.47-µF input ceramic capacitor. Additional input capacitance is required external to the module to handle the input ripple current of the application. This input capacitance must be very close to the module. Input capacitor selection is generally directed to satisfy the input ripple current requirements rather than by capacitance value. Worst-case input ripple current rating is dictated by Equation 8:

Equation 8.

where

• D ? V_O / V_IN

The worst-case ripple current occurs when the module is presented with full load current and when V_IN = (2 × V_O).

Recommended minimum input capacitance is 10-µF X7R ceramic with a voltage rating at least 25% higher than the maximum applied input voltage for the application. TI also recommends to pay attention to the voltage and temperature deratings of the capacitor selected.

If the system design requires a certain minimum value of input ripple voltage ΔV_IN be maintained then Equation 9 may be used.

If ΔV_IN is 1% of V_IN for a 24V input to 3.3V output application this equals 240 mV and f_SW = 400 kHz.

C_IN≥ 2 A × 3.3 V / 24V × (1– 3.3 V/24 V) / (400000 × 0.240 V)

≥ 2.5 μF

Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input capacitance and parasitic inductance of the incoming supply lines.

8.2.2.1.6 R_DS(on) Resistor Selection

Many designs begin with a desired switching frequency in mind. For that purpose Equation 10 can be used.

This can be rearranged as

The selection of RON and f_SW(CCM) must be confined by limitations in the ON-time and OFF-time for the Constant On-Time Control (COT) Circuit Overview section.

The ON-time of the LMZ14202 timer is determined by the resistor R_DS(on) and the input voltage V_IN. It is calculated as follows:

The inverse relationship of t_ON and V_IN gives a nearly constant switching frequency as V_IN is varied. Select an R_DS(on) level to fascilitate an ON-time at maximum V_IN is greater than 150 ns. The ON-timer has a limiter to ensure a minimum of 150 ns for t_ON. This function imits the maximum operating frequency, which is governed by Equation 13:

Use Equation 14 to select R_DS(on) a particular operating frequency while maintaining the minimum ON-time of 150 ns.

If R_DS(on) calculated in Equation 11 is less than the minimum value determined in Equation 14, select a lower frequency. Alternatively, V_IN(max) can also be limited to keep the frequency unchanged.

8.2.2.1.6.1 Discontinuous Conduction and Continuous Conduction Mode Selection

Operating frequency in DCM can be calculated as follows:

Equation 15. f_SW(DCM) ? V_O × (V_IN-1) × 10 μH × 1.18 × 10²⁰ × I_O/(V_IN–V_O) × R_DS(on) ²

In CCM, current flows through the inductor through the entire switching cycle and never falls to zero during the OFF-time. The switching frequency remains relatively constant with load current and line voltage variations. The CCM operating frequency can be calculated using Equation 7 above.

Following is a comparison pair of waveforms of the showing both CCM (upper) and DCM operating modes.

Figure 33. CCM and DCM Operating Modes
V_IN = 24 V, V_O = 3.3 V, I_O = 2 A/0.32 A 2 μs/div

The approximate formula for determining the DCM/CCM boundary is as follows:

Equation 16. I_DCB ? V_O × (V_IN– V_O)/(2 × 10 μH × f_SW(CCM) × V_IN)

Following is a typical waveform showing the boundary condition.

Figure 34. Transition Mode Operation
V_IN = 24 V, V_O = 3.3 V, I_O = 0.35 A 2 μsec/div

The inductor internal to the module is 10 μH. This value was chosen as a good balance between low and high input voltage applications. The main parameter affected by the inductor is the amplitude of the inductor ripple current (I_LR). I_LR can be calculated with:

Equation 17. I_{LR P-P} = V_O × (V_IN– V_O)/(10 µH × f_SW × V_IN)

where

• V_IN is the maximum input voltage and f_SW is determined from Equation 10.

If the output current I_O is determined by assuming that I_O = I_L, the higher and lower peak of I_LR can be determined. Be aware that the lower peak of I_LR must be positive if CCM operation is required.