ZHCSMU1G October 2020 – May 2024 LMR43610-Q1 , LMR43620-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY VOLTAGE (VIN PIN) | ||||||
| VINMIN | Input voltage rising threshold for start-up | Before start-up | 3.2 | 3.35 | 3.5 | V |
| Input voltage falling threshold | Once operating | 2.45 | 2.7 | 3 | V | |
| ISD(VIN) | Shutdown quiescent current at VIN pin | EN = 0V | 0.25 | 1 | μA | |
| IQVIN(nonsw) | Non-switching input current; measured at VIN pin (1) | Fixed 5.0V VOUT, VVOUT/FB = 5.25V | 1.6 | 3 | μA | |
| IQVIN(nonsw) | Non-switching input current; measured at VIN pin (1) | Fixed 3.3V VOUT, VVOUT/FB = 3.47V | 1.2 | 2.2 | μA | |
| ENABLE (EN PIN) | ||||||
| VEN-WAKE | EN wakeup threshold | 0.5 | 0.7 | 1 | V | |
| VEN-VOUT | Precision enable rising threshold for VOUT | 1.16 | 1.23 | 1.3 | V | |
| VEN-HYST | Enable hysteresis below VEN-VOUT | 0.3 | 0.35 | 0.4 | V | |
| ILKG-EN | Enable pin input leakage current | VEN = VIN = 13.5V | 10 | nA | ||
| INTERNAL LDO (VCC PIN) | ||||||
| VCC | VCC pin output voltage | VFB = 0V, IVCC = 1mA | 3.1 | 3.3 | 3.45 | V |
| VOLTAGE FEEDBACK (VOUT/FB PIN) | ||||||
| VOUT | Output voltage accuracy for fixed VOUT | 3.3V VOUT, VIN = 3.6V to 36V, FPWM Mode | 3.27 | 3.3 | 3.33 | V |
| VOUT | Output voltage accuracy for fixed VOUT | 5V VOUT, VIN = 5.5V to 36V, FPWM Mode | 4.94 | 5.00 | 5.06 | V |
| VFB | Internal reference voltage accuracy | VOUT = 1V, VIN = 3.0V to 36V, FPWM Mode | 0.99 | 1.00 | 1.01 | V |
| IFB(LKG) | FB input current | Adjustable configuration, FB = 1V | 10 | nA | ||
| CURRENT LIMITS | ||||||
| IPEAKMAX | High-side peak current limit | LMR43610-Q1 | 1.4 | 1.8 | 2.1 | A |
| IVALMAX | Low-side valley current limit | LMR43610-Q1 | 0.85 | 1.1 | 1.4 | A |
| IPEAKMIN | Minimum peak current limit | LMR43610-Q1, auto mode | 0.17 | 0.27 | 0.4 | A |
| INEGMIN | Low-side valley current negative limit | LMR43610-Q1, FPWM mode | -1 | -0.8 | -0.6 | A |
| IPEAKMAX | High-side peak current limit | LMR43620-Q1 | 2.8 | 3.4 | 3.9 | A |
| IVALMAX | Low-side valley current limit | LMR43620-Q1 | 1.9 | 2.2 | 2.53 | A |
| IPEAKMIN | Minimum peak current limit | LMR43620-Q1, auto mode | 0.37 | 0.5 | 0.65 | A |
| INEGMIN | Negative current limit | LMR43620-Q1, FPWM mode | -1 | -0.8 | -0.6 | A |
| IZC | Zero-cross current limit | Auto mode | 30 | 80 | 135 | mA |
| POWER GOOD (PGOOD PIN) | ||||||
| PGDOV | PGOOD upper threshold - rising | % of VOUT/FB (fixed or adj. output) | 104 | 108 | 111 | % |
| PGDUV | PGOOD upper threshold - falling | % of VOUT/FB (fixed or adj. output) | 89 | 91 | 94.2 | % |
| PGDHYST | PGOOD recovery hysteresis for OV | % of VOUT/FB target regulation voltage | 2 | 2.4 | 2.8 | % |
| PGOOD recovery hysteresis for UV | % of VOUT/FB target regulation voltage | 1.1 | 3.3 | 5.9 | % | |
| VPGD-VAL | Minimum VIN for PGOOD function | VEN = 0V, RPGD_PU = 10kΩ | 1.5 | V | ||
| RPGD | PGOOD ON resistance | VEN = 3.3V, 200μA pull up current | 100 | Ω | ||
| RPGD | PGOOD ON resistance | VEN = 0V, 200μA pull up current | 100 | Ω | ||
| tRESET_FILTER | PGOOD deglitch delay at falling edge | 25 | 40 | 75 | μs | |
| tPGOOD_ACT | Delay time to PGOOD high signal | 1.35 | 2.5 | 4 | ms | |
| SOFT START | ||||||
| tSS | Time from first SW pulse to VOUT/FB at 90% of set point. | 2 | 3.5 | 4.6 | ms | |
| tHICCUP | Time in hiccup before retry soft start | 30 | 50 | 75 | ms | |
| OSCILLATOR (SYNC/MODE PIN) | ||||||
| tPULSE_H | High duration needed to be recognized as a pulse | 100 | ns | |||
| tPULSE_L??? | Low duration needed to be recognized as a pulse | 100 | ns | |||
| tSYNC | High/Low level pulse maximum duration to be recognized as a valid clock signal | 6 | μs | |||
| tMODE | Time at one level needed to indicate FPWM or auto mode | 12.5 | μs | |||
| fSYNC | Frequency SYNC range | 0.2 | 2.5 | MHz | ||
| VMODE_L | SYNC/MODE input voltage low level threshold | 1 | V | |||
| VMODE_H | SYNC/MODE input voltage high level threshold | 1.6 | V | |||
| OSCILLATOR (RT PIN) | ||||||
| FSW(1MHz) | Switching frequency with internal fixed 1MHz setting | RT pin tie to VCC | 0.9 | 1 | 1.1 | MHz |
| FSW(2p2MHz) | Switching frequency with fixed 2.2MHz | RT pin tied to GND | 2.1 | 2.2 | 2.3 | MHz |
| FSW(Adj) | Accuracy of external frequency, 400kHz | RRT = 39.2kΩ 0.1% resistor | 0.34 | 0.4 | 0.46 | MHz |
| SPREAD SPECTRUM | ||||||
| DeltaFc | Frequency increase/decrease from spread spectrum of internal oscillator | DRSS | ±4 | % | ||
| SWITCH NODE | ||||||
| tON-MIN | Minimum HS switch on-time | FPWM mode IOUT = 1A, 2.2MHz fixed | 65 | 75 | ns | |
| tOFF-MIN | Minimum HS switch off-time | 60 | 85 | ns | ||
| tON-MAX | Maximum HS switch on-time | HS timeout in dropout | 6 | 9 | 13 | μs |
| POWER STAGE | ||||||
| VBOOT_UVLO | Voltage on BOOT pin compared to SW which will turnoff high-side switch | 2.1 | V | |||
| RDSON-HS | High-side MOSFET on-resistance | Load = 1A | 132 | 260 | mΩ | |
| RDSON-LS | Low-side MOSFET on-resistance | Load = 1A | 75 | 140 | mΩ | |