ZHCSP81B January 2022 – September 2023 LMR38010
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY VOLTAGE AND CURRENT | ||||||
| VIN_OPERATE | Input operating voltage | Needed to start up | 4.2 | V | ||
| Once operating | 3.8 | V | ||||
| IQ(Non-SW) | Non-switching quiescent current | VEN = 3.3 V (PFM variant only) | 40 | μA | ||
| ISD | Shutdown quiescent current; measured at VIN pin | VEN = 0 V | 3 | 10 | μA | |
| ENABLE | ||||||
| VEN-H | Enable input high level | VEN rising | 1.1 | 1.25 | 1.4 | V |
| VEN-L | Enable input low level | VEN falling | 0.95 | 1.10 | 1.22 | V |
| ILKG-EN | Enable input leakage current | VEN = 3.3V | 5.0 | nA | ||
| VOLTAGE REFERENCE (FB PIN) | ||||||
| VREF | Feedback reference voltage | Vin=4.2V to 80V, TJ=25°C, FPWM | 0.99 | 1 | 1.01 | V |
| VREF | Feedback reference voltage | FPWM | 0.985 | 1 | 1.015 | V |
| CURRENT LIMITS AND HICCUP | ||||||
| IHS-LIMIT | High-side current limit(2) | 1A Version | 1.3 | 1.6 | 1.9 | A |
| ILS-LIMIT | Low-side current limit(2) | 1A Version | 0.9 | 1.2 | 1.5 | A |
| IL-ZC | Zero cross detector threshold | PFM variants only | 0.01 | A | ||
| IPEAK-MIN | Minimum inductor peak current(2) | 1A Version, PFM variants only | 0.25 | A | ||
| IL-NEG | Negative current limit(2) | 1A Version, FPWM variant only | –0.5 | A | ||
| POWER STAGE | ||||||
| RDS-ON-HS | High-side MOSFET ON-resistance | 303 | mΩ | |||
| RDS-ON-LS | Low-side MOSFET ON-resistance | 133 | mΩ | |||
| tON-MIN | Minimum switch on-time(3) | VIN =24 V, Iout = 1 A | 80 | 131 | ns | |
| tOFF-MIN | Minimum switch off-time | 190 | 300 | ns | ||
| tON-MAX | Maximum switch on-time | 5 | us | |||
| SWITCHING FREQUENCY AND SYNCHRONIZATION | ||||||
| FOSC | Switching frequency | RT = 49.9 k? | 430 | 525 | 650 | kHz |
| FSPREAD | Spread of internal oscillator with Spread Spectrum Enabled |
-8 | 8 | % | ||
| VSYNC_HI | SYNC clock high level threshold | 2 | V | |||
| VSYNC_LO | SYNC clock low level threshold | 0.6 | V | |||
| tPULSE_H | High duration needed to be recognized as a pulse | 50 | ns | |||
| CLOCK | Time needed for clock to lock to a valid synchronization signal in sync cycles | 230 | us | |||
| STARTUP AND TRACKING | ||||||
| tSS | Internal soft-start time | 4 | ms | |||
| POWER GOOD | ||||||
| VPG-HIGH-UP | Power-Good upper threshold - rising | % of FB voltage | 110% | 112% | 114% | |
| VPG-LOW-DN | Power-Good lower threshold - falling | % of FB voltage | 90% | 92% | 94% | |
| VPG-HYS | Power-Good hysteresis (rising & falling) | % of FB voltage | 2.2% | |||
| VPG-VALID | Minimum input voltage for proper Power-Good function | 2 | V | |||
| RPG | Power-Good on-resistance | VEN = 0 V | 140 | Ω | ||
| RPG | Power-Good on-resistance | VEN = 3.3V | 92 | Ω | ||
| tPGDFLT(fall) | Glitch filter time constant for PGOOD function | 40 | us | |||
| THERMAL SHUTDOWN | ||||||
| TSD-Rising(4) | Thermal shutdown | Shutdown threshold | 163 | ℃ | ||
| TSD-Falling(4) | Thermal shutdown | Recovery threshold | 150 | ℃ | ||