ZHCSIN5D August 2018 – August 2022 LMR36006-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1
Design 1: Low Power 24-V, 600-mA PFM Converter
- 9.2.1.1 Design Requirements
- 9.2.1.2
Detailed Design Procedure
- 9.2.1.2.1 Custom Design With WEBENCH Tools
- 9.2.1.2.2 Choosing the Switching Frequency
- 9.2.1.2.3 Setting the Output Voltage
- 9.2.1.2.4 Inductor Selection
- 9.2.1.2.5 Output Capacitor Selection
- 9.2.1.2.6 Input Capacitor Selection
- 9.2.1.2.7 CBOOT
- 9.2.1.2.8 VCC
- 9.2.1.2.9 CFF Selection
- 9.2.1.2.10 Maximum Ambient Temperature
- 9.2.1.3 Application Curves
- 9.2.2 Design 2: High Density 12-V , 600-mA FPWM Converter
- 9.2.1
Design 1: Low Power 24-V, 600-mA PFM Converter
- 9.3 What to Do and What Not to Do
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8.3.1 Power-Good Flag Output
The power-good flag function (PG output pin) of the LMR36006-Q1 can be used to reset a system microprocessor whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation for short excursions of the output voltage, such as during line and load transients. Output voltage excursions lasting less than tPG do not trip the power-good flag. Power-good operation can best be understood by reference to Figure 8-2 and Figure 8-3. Note that during initial power-up, a delay of about 4 ms (typical) is inserted from the time that EN is asserted to the time that the power-good flag goes high. This delay only occurs during start-up and is not encountered during normal operation of the power-good function.
The power-good output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic supply. It can also be pulled up to either VCC or VOUT through an appropriate resistor as desired. If this function is not needed, the PG pin must be grounded. When EN is pulled low, the flag output is also forced low. With EN low, power good remains valid as long as the input voltage is ≥ 2 V (typical). Limit the current into this pin to ≤ 4 mA.
Figure 8-2 Static Power-Good Operation
Figure 8-3 Power-Good-Timing Behavior