ZHCSHQ4E February 2018 – November 2020 LMR33620
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Custom Design With WEBENCH? Tools
- 9.2.2.2 Choosing the Switching Frequency
- 9.2.2.3 Setting the Output Voltage
- 9.2.2.4 Inductor Selection
- 9.2.2.5 Output Capacitor Selection
- 9.2.2.6 Input Capacitor Selection
- 9.2.2.7 CBOOT
- 9.2.2.8 VCC
- 9.2.2.9 CFF Selection
- 9.2.2.10 External UVLO
- 9.2.2.11 Maximum Ambient Temperature
- 9.2.3 Application Curves
- 9.3 What to Do and What Not to Do
- 10Layout
- 11Device and Documentation Support
封裝選項(xiàng)
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RNX|12
- DDA|8
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購信息
8.3.1 Power-Good Flag Output
The power-good flag function (PG output pin) of the LMR33620 can be used to reset a system microprocessor whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation for short excursions of the output voltage, such as during line and load transients. The timing parameters of the glitch filter are found in Section 7.5. Output voltage excursions lasting less than tPG do not trip the power-good flag. Power-good operation can best be understood by reference to Figure 8-1 and Figure 8-2. Note that during initial power up, a delay of about 4 ms (typical) is inserted from the time that EN is asserted to the time that the power-good flag goes high. This delay only occurs during start-up and is not encountered during normal operation of the power-good function.
The power-good output consists of an open-drain NMOS, requiring an external pullup resistor to a suitable logic supply. It can also be pulled up to either VCC or VOUT, through a 100-kΩ resistor, as desired. If this function is not needed, the PG pin must be left floating. When EN is pulled low, the flag output is also forced low. With EN low, power good remains valid as long as the input voltage is ≥ 2 V (typical). Limit the current into the power-good flag pin to less than 5 mA D.C. The maximum current is internally limited to about 35 mA when the device is enabled and about 65 mA when the device is disabled. The internal current limit protects the device from any transient currents that can occur when discharging a filter capacitor connected to this output.
Figure 8-1 Static Power-Good Operation
Figure 8-2 Power-Good-Timing Behavior