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ZHCSHQ4E February 2018 – November 2020 LMR33620

PRODUCTION DATA

封裝選項

請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機械數(shù)據(jù) (封裝 | 引腳)

RNX|12
DDA|8

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

RNX|12
- QFND597B
DDA|8
- PPTD058J

訂購信息

7.5 Electrical Characteristics

Limits apply over the operating junction temperature (T_J) range of –40°C to +125°C, unless otherwise stated. Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most likely parametric norm at T_J = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: V_IN = 12 V, V_EN = 4 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE
V_IN	Minimum operating input voltage				3.8	V
I_Q	Non-switching input current; measured at VIN pin ⁽²⁾	V_FB = 1.2 V		24	34	μA
I_SD	Shutdown quiescent current; measured at VIN pin	EN = 0		5	10	μA
ENABLE
V_EN-VCC-H	EN input level required to turn on internal LDO	Rising threshold			1	V
V_EN-VCC-L	EN input level required to turn off internal LDO	Falling threshold	0.3			V
V_EN-H	EN input level required to start switching	Rising threshold	1.2	1.231	1.26	V
V_EN-HYS	Hysteresis below V_EN-H	Hysteresis below V_EN-H; falling		100		mV
I_LKG-EN	Enable input leakage current	V_EN = 3.3 V		0.2		nA
INTERNAL SUPPLIES
VCC	Internal LDO output voltage appearing at the VCC pin	6 V ≤ V_IN ≤ 36 V	4.75	5	5.25	V
V_BOOT-UVLO	Bootstrap voltage undervoltage lock-out threshold⁽³⁾			2.2		V
VOLTAGE REFERENCE (FB PIN)
V_FB	Feedback voltage; ADJ option		0.985	1	1.015	V
I_FB	Current into FB pin; ADJ option	FB = 1 V		0.2	50	nA
CURRENT LIMITS⁽⁴⁾
I_SC	High-side current limit	LMR33620	2.9	3.5	4	A
I_LIMIT	Low-side current limit	LMR33620	1.95	2.45	2.9	A
I_PEAK-MIN	Minimum peak inductor current	LMR33620		0.54		A
I_ZC	Zero current detector threshold			-0.106		A
SOFT START
t_SS	Internal soft-start time		2.9	4	6	ms
POWER GOOD (PG PIN)
V_PG-HIGH-UP	Power-good upper threshold - rising	% of FB voltage	105%	107%	110%
V_PG-HIGH-DN	Power-good upper threshold - falling	% of FB voltage	103%	105%	108%
V_PG-LOW-UP	Power-good lower threshold - rising	% of FB voltage	92%	94%	97%
V_PG-LOW-DN	Power-good lower threshold - falling	% of FB voltage	90%	92%	95%
t_PG	Power-good glitch filter delay⁽¹⁾		60		170	μs
R_PG	Power-good flag R_DSON	V_IN = 12 V, V_EN = 4 V		76	150	?
R_PG	Power-good flag R_DSON	V_EN = 0 V		35	60	?
V_IN-PG	Minimum input voltage for proper PG function	50-μA, EN = 0 V			2	V
V_PG	PG logic low output	50-μA, EN = 0 V, V_IN = 2V			0.2	V
OSCILLATOR
?_SW	Switching frequency	"A" Version	340	400	460	kHz
?_SW	Switching frequency	"B" Version	1.2	1.4	1.6	MHz
?_SW	Switching frequency	"C" Version, DDA package	1.8	2.1	2.4	MHz
?_SW	Switching frequency	"C" Version, RNX package	1.8	2.1	2.3	MHz
MOSFETS
R_DS-ON-HS	High-side MOSFET ON-resistance	RNX package		75	145	mΩ
R_DS-ON-HS	High-side MOSFET ON-resistance	DDA package		95	160	mΩ
R_DS-ON-LS	Low-side MOSFET ON-resistance	RNX package		50	95	mΩ
R_DS-ON-LS	Low-side MOSFET ON-resistance	DDA package		66	110	mΩ

(1) See Power-Good Flag Output for details.

(2) This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.

(3) When the voltage across the C_BOOT capacitor falls below this voltage, the low side MOSFET is turned on to recharge C_BOOT.

(4) The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.