The output capacitor or capacitors, C_OUT, must be chosen with care since it directly affects the steady state output voltage ripple, loop stability and the voltage overshoot and undershoot during load current transients.

The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going through the Equivalent Series Resistance (ESR) of the output capacitors:

Equation 11.

The other is caused by the inductor current ripple charging and discharging the output capacitors:

Equation 12.

The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the sum of two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltage regulation with presence of large current steps and fast slew rate. When a fast large load increase happens, output capacitors provide the required charge before the inductor current can slew up to the appropriate level. The control loop of the regulator usually needs three or more clock cycles to respond to the output voltage droop. The output capacitance must be large enough to supply the current difference for three clock cycles to maintain the output voltage within the specified range. Equation 13 shows the minimum output capacitance needed for specified output undershoot. When a sudden large load decrease happens, the output capacitors absorb energy stored in the inductor. The catch diode cannot sink current so the energy stored in the inductor results in an output voltage overshoot. Equation 14 calculates the minimum capacitance required to keep the voltage overshoot within a specified range.

Equation 13.

Equation 14.

where

• K_IND = Ripple ratio of the inductor ripple current (Δi_L / I_OUT)
• I_OL = Low level output current during load transient
• I_OH = High level output current during load transient
• V_US = Target output voltage undershoot
• V_OS = Target output voltage overshoot

For this design example, the target output ripple is 50 mV. Presuppose ΔV_{OUT_ESR} = ΔV_{OUT_C} = 50 mV, and chose K_IND = 0.4. Equation 11 yields ESR no larger than 41.7 m? and Equation 12 yields C_OUT no smaller than 6 μF. For the target overshoot and undershoot range of this design, V_US = V_OS = 5% × V_OUT = 250 mV. The C_OUT can be calculated to be no smaller than 64.8 μF and 6.4 μF by Equation 13 and Equation 14 respectively. In summary, the most stringent criteria for the output capacitor is 100 μF. For this design example, two 47-μF, 16-V, X7R ceramic capacitors with 5-m? ESR are used in parallel.