ZHCSP13A september 2021 – june 2023 LMK1D1204P
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| POWER SUPPLY CHARACTERISTICS | ||||||
| IDDSTAT | LMK1D1204P | All-outputs enabled and unterminated, f = 0 Hz (1) | 50 | mA | ||
| IDD100M | LMK1D1204P | All-outputs enabled, RL = 100 Ω, f =100 MHz | 60 | 72 | mA | |
| INPUT CHARACTERISTICS (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%) | ||||||
| VdI3 | 3-state input | Open | 0.4 × VCC | V | ||
| VIH | Input high voltage | Minimum input voltage for a logical "1" state | 0.7 × VCC | VCC + 0.3 | V | |
| VIL | Input low voltage | Maximum input voltage for a logical "0" state | –0.3 | 0.3 × VCC | V | |
| IIH | Input high current | VDD can be 1.8V/2.5V/3.3V with VIH = VDD | 30 | μA | ||
| IIL | Input low current | VDD can be 1.8V/2.5V/3.3V with VIH = VDD | –30 | μA | ||
| Rpull-up(EN) | Input pullup resistor | 500 | kΩ | |||
| Rpull-down(EN) | Input pulldown resistor | 320 | kΩ | |||
| SINGLE-ENDED LVCMOS/LVTTL CLOCK INPUT (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%) | ||||||
| fIN | Input frequency | Clock input | DC | 250 | MHz | |
| VIN_S-E | Single-ended Input Voltage Swing | Assumes a square wave input with two levels | 0.4 | 3.465 | V | |
| dVIN/dt | Input Slew Rate (20% to 80% of the amplitude) | 0.05 | V/ns | |||
| IIH | Input high current | VDD = 3.465 V, VIH = 3.465 V | 50 | μA | ||
| IIL | Input low current | VDD = 3.465 V, VIL = 0 V | –30 | μA | ||
| CIN_SE | Input capacitance | at 25°C | 3.5 | pF | ||
| DIFFERENTIAL CLOCK INPUT (Applies to VDD = 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%) | ||||||
| fIN | Input frequency | Clock input | 2 | GHz | ||
| VIN,DIFF(p-p) | Differential input voltage peak-to-peak {2*(VINP-VINN)} | VICM = 1 V (VDD = 1.8 V) | 0.3 | 2.4 | VPP | |
| VICM = 1.25 V (VDD = 2.5 V/3.3 V) | 0.3 | 2.4 | ||||
| VICM | Input common mode voltage | VIN,DIFF(P-P) > 0.4 V (VDD = 1.8 V/2.5/3.3 V) | 0.25 | 2.3 | V | |
| IIH | Input high current | VDD = 3.465 V, VINP = 2.4 V, VINN = 1.2 V | 30 | μA | ||
| IIL | Input low current | VDD = 3.465 V, VINP = 0 V, VINN = 1.2 V | –30 | μA | ||
| CIN_S-E | Input capacitance (Single-ended) | at 25°C | 3.5 | pF | ||
| LVDS DC OUTPUT CHARACTERISTICS | ||||||
| |VOD| | Differential output voltage magnitude |VOUTP - VOUTN| | VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω | 250 | 350 | 450 | mV |
| ΔVOD | Change in differential output voltage magnitude. Per output, defined as the difference between VOD in logic hi/lo states. | VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω | –15 | 15 | mV | |
| VOC(SS) | Steady-state common mode output voltage | VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω (VDD = 1.8 V) | 1 | 1.2 | V | |
| VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω (VDD = 2.5 V/3.3 V) | 1.1 | 1.375 | ||||
| ΔVOC(SS) | Change in steady-state common mode output voltage. Per output, defined as the difference in VOC in logic hi/lo states. | VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω | –15 | 15 | mV | |
| LVDS AC OUTPUT CHARACTERISTICS | ||||||
| Vring | Output overshoot and undershoot | VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω, fOUT = 491.52 MHz | –0.1 | 0.1 | VOD | |
| VOS | Output AC common mode | VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω | 50 | 100 | mVpp | |
| IOS | Short-circuit output current (differential) | VOUTP = VOUTN | –12 | 12 | mA | |
| IOS(cm) | Short-circuit output current (common-mode) | VOUTP = VOUTN = 0 | –24 | 24 | mA | |
| tPD | Propagation delay | VIN,DIFF(P-P) = 0.3 V, RLOAD = 100 Ω (2) | 0.3 | 0.575 | ns | |
| tSK, O | Output skew | Skew between outputs with the same load conditions | 20 | ps | ||
| tSK, PP | Part-to-part skew | Skew between outputs on different parts subjected to the same operating conditions with the same input and output loading. | 250 | ps | ||
| tSK, P | Pulse skew | 50% duty cycle input, crossing point-to-crossing-point distortion (4) | –20 | 20 | ps | |
| tRJIT(ADD) | Random additive Jitter (rms) | fIN = 156.25 MHz with 50% duty-cycle, Input slew rate = 1.5V/ns, Integration range = 12 kHz – 20 MHz, with output load RLOAD = 100 Ω | 50 | 60 | fs, RMS | |
| Phase noise | Phase Noise for a carrier frequency of 156.25 MHz with 50% duty-cycle, Input slew rate = 1.5V/ns with output load RLOAD = 100 Ω | PN1kHz | –143 | dBc/Hz | ||
| PN10kHz | –152 | |||||
| PN100kHz | –157 | |||||
| PN1MHz | –160 | |||||
| PNfloor | –164 | |||||
| MUXISO | Mux Isolation | fIN = 156.25 MHz. The difference in power level at fIN when the selected clock is active and the unselected clock is static versus when the selected clock is inactive and the unselected clock is active. | 80 | dB | ||
| ODC | Output duty cycle | With 50% duty cycle input | 45 | 55 | % | |
| tR/tF | Output rise and fall time | 20% to 80% with RLOAD = 100 Ω | 300 | ps | ||
| VAC_REF | Reference output voltage | VDD = 2.5 V, ILOAD = 100 μA | 0.9 | 1.25 | 1.375 | V |
| POWER SUPPLY NOISE REJECTION (PSNR) VDD = 2.5 V/ 3.3 V | ||||||
| PSNR | Power Supply Noise Rejection (fcarrier = 156.25 MHz) | 10 kHz, 100 mVpp ripple injected on VDD | –70 | dBc | ||
| 1 MHz, 100 mVpp ripple injected on VDD | –50 | |||||