ZHCSP13A september 2021 – june 2023 LMK1D1204P
PRODUCTION DATA
See Input Termination for proper input terminations, dependent on single-ended or differential inputs.
See LVDS Output Termination for output termination schemes depending on the receiver application.
Unused outputs can be disabled using the corresponding OEx pin setting according to Table 9-2. Disabling the outputs also eliminates requirement of termination resistors.
In this example, the PHY, ASIC, FPGA and CPU require different schemes. Power supply filtering and bypassing is critical for low-noise applications.
See Power Supply Recommendations for recommended filtering techniques. A reference layout is provided in Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board user's guide (SCAU043).