SNAS489K March 2011 – December 2014 LMK04803 , LMK04805 , LMK04806 , LMK04808
PRODUCTION DATA.
All Vcc pins must always be connected.
Integrated capacitance on the LMK0480x makes external high frequency decoupling capacitors (≤ 1 nF) unnecessary. The internal capacitance is more effective at filtering high frequency noise than off device bypass capacitance because there is no bond wire inductance between the LMK0480x circuit and the bypass capacitor.
Each of these pins has an internal 200 pF of capacitance.
Ferrite beads may be used to reduce crosstalk between different clock output frequencies on the same LMK0480x device. Ferrite beads placed between the power supply and a clock Vcc pin will reduce noise between the Vcc pin and the power supply. When several output clocks share the same frequency a single ferrite bead can be used between the power supply and each same frequency CLKout Vcc pin.
When using ferrite beads on CLKout Vcc pins, consider the following guidelines to ensure the power supply will source the needed switching current:
Each of these pins has internal bypass capacitance.
Ferrite beads should not be used between these pins and the power supply/large bypass capacitors because these Vcc pins don’t produce much noise and a ferrite bead can cause phase noise disturbances and resonances.
The typical application diagram in Figure 40 shows all these Vccs connected to together to Vcc without a ferrite bead.
Each of these pins has an internal bypass capacitor.
Use of a ferrite bead between the power supply/large bypass capacitors and PLL1 is optional. PLL1 charge pump can be connected directly to Vcc along with Vcc1, Vcc4, and Vcc9. Depending on the application, a 0.1 uF capacitor may be placed close to PLL1 charge pump Vcc pin.
A ferrite bead should be placed between the power supply/large bypass capacitors and Vcc8. Most applications have high PLL2 phase detector frequencies and (> 50 MHz) such that the internal bypassing is sufficient and a ferrite bead can be used to isolate this switching noise from other circuits. For lower phase detector frequencies a ferrite bead is optional and depending on application a 0.1 uF capacitor may be added on Vcc8.
Each of these pins has an internal 100 pF of capacitance. No ferrite bead should be placed between the power supply/large bypass capacitors and Vcc5 or Vcc7.
These pins are unique since they supply an output clock and other circuitry.
Vcc5 supplies CLKin and OSCout1.
Vcc7 supplies OSCin, OSCout0, and PLL2 circuitry.
Impacts of excessive noise on PLL2 circuitry may impact PLL2 DLD operation.
It is recommended to use a complementary LVCMOS output format such as LVCMOS (Norm/Inv) to reduce switching noise and crosstalk when using LVCMOS. If only a single LVCMOS output is required, the complementary LVCMOS output format can still be used by leaving the unused LVCMOS output floating.
When using an LVPECL output it is not recommended to place a capacitor to ground on the output as might be done when using a capacitor input LC lowpass filter. The capacitor will appear as a short to the LVPECL output drivers which are able to supply large amounts of switching current. The effect of the LVPECL sourcing large switching currents can result in:
Leave unused clock outputs floating and powered down.
Unused clock inputs can be left floating.
The LDObyp1 and LDObyp2 pins should be connected to GND through external capacitors, as shown in Figure 40.
From Table 127 the current consumption can be calculated for any configuration.
For example, the current for the entire device with 1 LVDS (CLKout0) and 1 LVPECL 1.6 Vpp /w 240-Ω emitter resistors (CLKout1) output active with a clock output divide = 1, and no other features enabled can be calculated by adding up the following blocks: core current, clock buffer, one LVDS output buffer current, and one LVPECL output buffer current. There will also be one LVPECL output drawing emitter current, which means some of the power from the current draw of the device is dissipated in the external emitter resistors which doesn't add to the power dissipation budget for the device but is important for LDO ICC calculations.
For total current consumption of the device, add up the significant functional blocks. In this example, 228.1 mA equals the sum of the following:
Once total current consumption has been calculated, power dissipated by the device can be calculated. The power dissipation of the device is equation to the total current entering the device multiplied by the voltage at the device minus the power dissipated in any emitter resistors connected to any of the LVPECL outputs. If no emitter resistors are connected to the LVPECL outputs, this power will be 0 watts. Continuing the above example which has 228.1 mA total Icc and one output with 240-Ω emitter resistors. Total IC power = 717.7 mW = 3.3 V * 228.1 mA - 35 mW.
| BLOCK | CONDITION | TYPICAL ICC
(mA) |
POWER DISSIPATED in DEVICE (mW) |
POWER DISSIPATED EXTERNALLY(1)(2)(3)
(mW) |
|
|---|---|---|---|---|---|
| CORE and FUNCTIONAL BLOCKS | |||||
| Core | MODE = 0: Dual Loop, Internal VCO | PLL1 and PLL2 locked | 140 | 462 | - |
| MODE = 2: Dual Loop, Internal VCO, 0-Delay | PLL1 and PLL2 locked; Includes EN_FEEDBACK_MUX = 1 | 155 | 512 | - | |
| MODE = 3: Dual Loop, External VCO | PLL1 and PLL2 locked | 127 | 419 | - | |
| MODE = 6: Single Loop (PLL2), Internal VCO | PLL2 locked | 116 | 383 | - | |
| MODE = 11: Single Loop (PLL2), External VCO | PLL2 locked | 103 | 340 | - | |
| MODE = 15: Dual PLL, 0-DELAY, External VCO | 144 | 475 | |||
| MODE = 16: Clock Distribution | PD_OSCin = 0 | 42 | 139 | - | |
| PD_OSCin = 1 | 34.5 | 114 | - | ||
| EN_TRACK | Tracking is enabled (EN_TRACK = 1) | 2 | 6.6 | - | |
| Base Clock Distribution | At least 1 CLKoutX_Y_PD = 0 | 17.3 | 57.1 | - | |
| CLKout Group | Each CLKout group (CLKout0/1 and 10/11, CLKout2/3 and 4/5, CLKout 6/7 and 8/9) | 2.8 | 9.2 | - | |
| Clock Divider/ Digital Delay |
When a clock output is enabled, this contributes the divider/delay block | 25.5 | 84.1 | - | |
| Divider / digital delay in extended mode | 29.6 | 97.7 | - | ||
| VCO Divider | VCO Divider current | 7.7 | 25.4 | - | |
| HOLDOVER mode | When in holdover mode | 2.2 | 7.2 | - | |
| Feedback Mux | Feedback mux must be enabled for 0-delay modes and digital delay mode (SYNC_QUAL = 1) | 4.9 | 16.1 | - | |
| SYNC Asserted | While SYNC is asserted, this extra current is drawn | 1.7 | 5.6 | - | |
| EN_SYNC = 1 | Required for SYNC functionality. May be turned off once SYNC is complete to save power. | 6 | 19.8 | - | |
| SYNC_QUAL = 1 | Delay enabled, delay > 7 (CLKout_MUX = 2, 3) | 8.7 | 28.7 | - | |
| Crystal Mode | Enabling the Crystal Oscillator | XTAL_LVL = 0 | 1.8 | 5.9 | - |
| XTAL_LVL = 1 | 2.7 | 9 | - | ||
| XTAL_LVL = 2 | 3.6 | 12 | - | ||
| XTAL_LVL = 3 | 4.5 | 15 | - | ||
| OSCin Doubler | EN_PLL2_REF_2X = 1 | 2.8 | 9.2 | - | |
| Analog Delay | Analog Delay Value | CLKoutX_Y_ANLG_DLY = 0 to 3 | 3.4 | 11.2 | - |
| CLKoutX_Y_ANLG_DLY = 4 to 7 | 3.8 | 12.5 | - | ||
| CLKoutX_Y_ANLG_DLY = 8 to 11 | 4.2 | 13.9 | - | ||
| CLKoutX_Y_ANLG_DLY = 12 to 15 | 4.7 | 15.5 | - | ||
| CLKoutX_Y_ANLG_DLY = 16 to 23 | 5.2 | 17.2 | - | ||
| Only Single Output Of Clock Pair Has Analog Delay Selected. Example: CLKout0_ADLY_SEL = 1 and CLKout1_ADLY_SEL = 0, or CLKout0_ADLY_SEL = 0 and CLKout1_ADLY_SEL = 1. |
2.8 | 9.2 | - | ||
| CLOCK OUTPUT BUFFERS | |||||
| LVDS | 100-Ω differential termination | 14.3 | 47.2 | - | |
| LVPECL | LVPECL 2.0 Vpp, AC coupled using 240-Ω emitter resistors | 32 | 70.6 | 35 | |
| LVPECL 1.6 Vpp, AC coupled using 240-Ω emitter resistors | 31 | 67.3 | 35 | ||
| LVPECL 1.6 Vpp, AC coupled using 120-Ω emitter resistors | 46 | 91.8 | 60 | ||
| LVPECL 1.2 Vpp, AC coupled using 240-Ω emitter resistors | 30 | 59 | 40 | ||
| LVPECL 0.7 Vpp, AC coupled using 240-Ω emitter resistors | 29 | 55.7 | 40 | ||
| LVCMOS | LVCMOS Pair (CLKoutX_TYPE = 6 to 9) CL = 5 pF |
3 MHz | 24 | 79.2 | - |
| 30 MHz | 26.5 | 87.5 | - | ||
| 150 MHz | 36.5 | 120.5 | - | ||
| LVCMOS Single (CLKoutX_TYPE = 10 to 13) CL = 5 pF |
3 MHz | 15 | 49.5 | - | |
| 30 MHz | 16 | 52.8 | - | ||
| 150 MHz | 21.5 | 71 | - | ||